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-- Copyright (C) 2001 Bill Billowitch.
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-- Some of the work to develop this test suite was done with Air Force
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-- support.  The Air Force and Bill Billowitch assume no
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-- responsibilities for this software.
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: tc1010.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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PACKAGE c06s03b00x00p10n01i01010pkg IS
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--
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--  This packages contains declarations of User attributes
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--
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-- ----------------------------------------------------------------------
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--
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  TYPE RESISTANCE IS RANGE 0 TO 1E9
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    UNITS
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      pf;
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      nf = 1000 pf;
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      mf = 1000 nf;
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    END UNITS;
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  TYPE t_logic IS (
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    U,  D,
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    Z0, Z1, ZDX, DZX, ZX,
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    W0, W1, WZ0, WZ1, WDX, DWX, WZX, ZWX, WX,
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    R0, R1, RW0, RW1, RZ0, RZ1, RDX, DRX, RZX, ZRX, RWX, WRX, RX,
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    F0, F1, FR0, FR1, FW0, FW1, FZ0, FZ1, FDX, DFX, FZX, ZFX, FWX, WFX, FRX, RFX, FX
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    );
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--
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--          Scalar types Declarations
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--
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  SUBTYPE st_scl1 IS BOOLEAN;
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  SUBTYPE st_scl2 IS BIT;
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  SUBTYPE st_scl3 IS CHARACTER;
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  SUBTYPE st_scl4 IS INTEGER;
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  SUBTYPE st_scl5 IS REAL;
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  SUBTYPE st_scl6 IS TIME;
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  SUBTYPE st_scl7 IS RESISTANCE;
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  SUBTYPE st_scl8 IS t_logic;
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--
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--          character string types
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--
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  SUBTYPE st_str1 IS STRING;
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  SUBTYPE st_str2 IS STRING (1 TO 4);
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--
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--          Scalar types with a range constraint
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--
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  SUBTYPE cst_scl1 IS BOOLEAN    RANGE  TRUE   TO      TRUE;
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  SUBTYPE cst_scl2 IS BIT        RANGE   '0'   TO       '0';
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  SUBTYPE cst_scl3 IS CHARACTER  RANGE   'a'   TO       'z';
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  SUBTYPE cst_scl4 IS INTEGER    RANGE    10 DOWNTO       0;
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  SUBTYPE cst_scl5 IS REAL       RANGE   0.0   TO      10.0;
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  SUBTYPE cst_scl6 IS TIME       RANGE  0 fs   TO     10 ns;
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  SUBTYPE cst_scl7 IS RESISTANCE RANGE  0 pf   TO  10000 pf;
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  SUBTYPE cst_scl8 IS t_logic    RANGE    F0   TO        FX;
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-- -----------------------------------------------------------------------------------------
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--      Attribute Declarations
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-- -----------------------------------------------------------------------------------------
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--
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  ATTRIBUTE atr_scl1 : st_scl1;
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  ATTRIBUTE atr_scl2 : st_scl2;
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  ATTRIBUTE atr_scl3 : st_scl3;
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  ATTRIBUTE atr_scl4 : st_scl4;
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  ATTRIBUTE atr_scl5 : st_scl5;
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  ATTRIBUTE atr_scl6 : st_scl6;
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  ATTRIBUTE atr_scl7 : st_scl7;
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  ATTRIBUTE atr_scl8 : st_scl8;
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  ATTRIBUTE atr_str1 : st_str1;
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  ATTRIBUTE atr_str2 : st_str2;
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  ATTRIBUTE cat_scl1 : cst_scl1;
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  ATTRIBUTE cat_scl2 : cst_scl2;
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  ATTRIBUTE cat_scl3 : cst_scl3;
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  ATTRIBUTE cat_scl4 : cst_scl4;
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  ATTRIBUTE cat_scl5 : cst_scl5;
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  ATTRIBUTE cat_scl6 : cst_scl6;
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  ATTRIBUTE cat_scl7 : cst_scl7;
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  ATTRIBUTE cat_scl8 : cst_scl8; 
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END;
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USE WORK.c06s03b00x00p10n01i01010pkg.all;
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ENTITY c06s03b00x00p10n01i01010ent IS
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END c06s03b00x00p10n01i01010ent;
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USE WORK.c06s03b00x00p10n01i01010pkg.all;
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ENTITY c06s03b00x00p10n01i01010ent_a IS
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  GENERIC (  gene_1 : cst_scl7;
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             gene_2 : st_str2   );
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  PORT (  port_1 : cst_scl7;
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          port_2 : st_str2   );
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--
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  ATTRIBUTE atr_scl1 OF port_1: SIGNAL IS      TRUE;
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  ATTRIBUTE atr_scl2 OF port_1: SIGNAL IS       '0';
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  ATTRIBUTE atr_scl3 OF port_1: SIGNAL IS       'z';
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  ATTRIBUTE atr_scl4 OF port_1: SIGNAL IS         0;
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  ATTRIBUTE atr_scl5 OF port_1: SIGNAL IS      10.0;
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  ATTRIBUTE atr_scl6 OF port_1: SIGNAL IS     10 ns;
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  ATTRIBUTE atr_scl7 OF port_1: SIGNAL IS  10000 pf;
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  ATTRIBUTE atr_scl8 OF port_1: SIGNAL IS        FX;
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  ATTRIBUTE atr_str1 OF port_1: SIGNAL IS  "signal";
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  ATTRIBUTE atr_str2 OF port_1: SIGNAL IS    "XXXX";
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--
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  ATTRIBUTE cat_scl1 OF port_1: SIGNAL IS      TRUE;
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--
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  ATTRIBUTE atr_scl1 OF port_2: SIGNAL IS      TRUE;
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  ATTRIBUTE atr_str1 OF port_2: SIGNAL IS  "signal";
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  ATTRIBUTE atr_str2 OF port_2: SIGNAL IS    "XXXX";
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  ATTRIBUTE cat_scl1 OF port_2: SIGNAL IS      TRUE;
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--
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  ATTRIBUTE atr_scl1 OF gene_1: CONSTANT IS      TRUE;
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  ATTRIBUTE atr_str1 OF gene_1: CONSTANT IS  "signal";
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  ATTRIBUTE atr_str2 OF gene_1: CONSTANT IS    "XXXX";
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  ATTRIBUTE cat_scl1 OF gene_1: CONSTANT IS      TRUE;
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--
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  ATTRIBUTE atr_scl1 OF gene_2: CONSTANT IS      TRUE;
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  ATTRIBUTE atr_str1 OF gene_2: CONSTANT IS  "signal";
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  ATTRIBUTE atr_str2 OF gene_2: CONSTANT IS    "XXXX";
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  ATTRIBUTE cat_scl1 OF gene_2: CONSTANT IS      TRUE;
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END c06s03b00x00p10n01i01010ent_a;
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-----------------------------------------------------------------------
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-- ARCHITECTURAL DECLARATION
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-----------------------------------------------------------------------
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ARCHITECTURE c06s03b00x00p10n01i01010arch_a OF c06s03b00x00p10n01i01010ent_a IS
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  SIGNAL sign_1 : cst_scl7;
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  SIGNAL sign_2 : st_str2;
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--
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  ATTRIBUTE atr_scl1 OF sign_1: SIGNAL IS      TRUE;
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  ATTRIBUTE atr_scl2 OF sign_1: SIGNAL IS       '0';
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  ATTRIBUTE atr_scl3 OF sign_1: SIGNAL IS       'z';
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  ATTRIBUTE atr_scl4 OF sign_1: SIGNAL IS         0;
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  ATTRIBUTE atr_scl5 OF sign_1: SIGNAL IS      10.0;
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  ATTRIBUTE atr_scl6 OF sign_1: SIGNAL IS     10 ns;
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  ATTRIBUTE atr_scl7 OF sign_1: SIGNAL IS  10000 pf;
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  ATTRIBUTE atr_scl8 OF sign_1: SIGNAL IS        FX;
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  ATTRIBUTE atr_str1 OF sign_1: SIGNAL IS  "signal";
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  ATTRIBUTE atr_str2 OF sign_1: SIGNAL IS    "XXXX";
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--
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  ATTRIBUTE cat_scl1 OF sign_1: SIGNAL IS      TRUE;
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--
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  ATTRIBUTE atr_scl1 OF sign_2: SIGNAL IS      TRUE;
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  ATTRIBUTE atr_str1 OF sign_2: SIGNAL IS  "signal";
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  ATTRIBUTE atr_str2 OF sign_2: SIGNAL IS    "XXXX";
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  ATTRIBUTE cat_scl1 OF sign_2: SIGNAL IS      TRUE;
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--
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BEGIN
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  TESTING: PROCESS
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  BEGIN
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    assert NOT(    port_1'atr_scl1 =      TRUE    and 
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                   port_1'atr_scl2 =       '0'    and 
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                   port_1'atr_scl3 =       'z'    and 
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                   port_1'atr_scl4 =         0    and 
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                   port_1'atr_scl5 =      10.0    and 
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                   port_1'atr_scl6 =     10 ns    and 
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                   port_1'atr_scl7 =  10000 pf    and 
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                   port_1'atr_scl8 =        FX    and 
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                   port_1'atr_str1 =  "signal"    and 
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                   port_1'atr_str2 =    "XXXX"    and 
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                   port_1'cat_scl1 =      TRUE    and 
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                   port_2'atr_scl1 =      TRUE    and 
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                   port_2'atr_str1 =  "signal"    and 
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                   port_2'atr_str2 =    "XXXX"    and 
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                   port_2'cat_scl1 =      TRUE    and 
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                   gene_1'atr_scl1 =      TRUE    and 
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                   gene_1'atr_str1 =  "signal"    and 
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                   gene_1'atr_str2 =    "XXXX"    and 
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                   gene_1'cat_scl1 =      TRUE    and 
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                   gene_2'atr_scl1 =      TRUE    and 
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                   gene_2'atr_str1 =  "signal"    and 
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                   gene_2'atr_str2 =    "XXXX"    and 
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                   gene_2'cat_scl1 =      TRUE )   
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      report "***PASSED TEST: c06s03b00x00p10n01i01010"
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      severity NOTE;
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    assert (    port_1'atr_scl1 =      TRUE    and 
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                port_1'atr_scl2 =       '0'    and 
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                port_1'atr_scl3 =       'z'    and 
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                port_1'atr_scl4 =         0    and 
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                port_1'atr_scl5 =      10.0    and 
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                port_1'atr_scl6 =     10 ns    and 
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                port_1'atr_scl7 =  10000 pf    and 
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                port_1'atr_scl8 =        FX    and 
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                port_1'atr_str1 =  "signal"    and 
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                port_1'atr_str2 =    "XXXX"    and 
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                port_1'cat_scl1 =      TRUE    and 
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                port_2'atr_scl1 =      TRUE    and 
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                port_2'atr_str1 =  "signal"    and 
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                port_2'atr_str2 =    "XXXX"    and 
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                port_2'cat_scl1 =      TRUE    and 
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                gene_1'atr_scl1 =      TRUE    and 
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                gene_1'atr_str1 =  "signal"    and 
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                gene_1'atr_str2 =    "XXXX"    and 
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                gene_1'cat_scl1 =      TRUE    and 
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                gene_2'atr_scl1 =      TRUE    and 
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                gene_2'atr_str1 =  "signal"    and 
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                gene_2'atr_str2 =    "XXXX"    and 
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                gene_2'cat_scl1 =      TRUE )   
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      report "***FAILED TEST: c06s03b00x00p10n01i01010 - An expanded name denotes an entity, the prefix denotes a construct that is ports, signals and generics." 
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      severity ERROR;
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    wait;
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  END PROCESS TESTING;
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END c06s03b00x00p10n01i01010arch_a;
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ARCHITECTURE c06s03b00x00p10n01i01010arch OF c06s03b00x00p10n01i01010ent IS
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  COMPONENT c06s03b00x00p10n01i01010ent_a
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    GENERIC (  gene_1 : cst_scl7;
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               gene_2 : st_str2   );
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    PORT (  port_1 : cst_scl7;
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            port_2 : st_str2   );
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  END COMPONENT;
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  FOR  SUB : c06s03b00x00p10n01i01010ent_a USE ENTITY work.c06s03b00x00p10n01i01010ent_a(c06s03b00x00p10n01i01010arch_a);
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  SIGNAL s1 : cst_scl7;
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  SIGNAL s2 : st_str2;
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BEGIN
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  SUB : c06s03b00x00p10n01i01010ent_a GENERIC MAP ( 10 pf, "ABCD" )
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    PORT MAP (    s1,    s2 ); 
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END c06s03b00x00p10n01i01010arch;
(10-10/2088)