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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: util_pk_test.vhd,v 1.2 2001-10-24 23:31:00 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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library ieee;  
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use ieee.std_logic_1164.all;
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package stimulus_generators is
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  procedure all_possible_values ( signal bv : out bit_vector;
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				  delay_between_values : in delay_length );
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  procedure all_possible_values ( signal bv : out std_ulogic_vector;
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				  delay_between_values : in delay_length );
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  procedure all_possible_values ( signal bv : out std_logic_vector;
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				  delay_between_values : in delay_length );
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end package stimulus_generators;
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package body stimulus_generators is
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  type digit_table is array ( natural range 0 to 1 ) of bit;
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  constant digit : digit_table := ( '0', '1' );
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  function natural_to_bv ( nat : in natural;
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      	      	      	   length : in natural ) return bit_vector is
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    variable temp : natural := nat;
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    variable result : bit_vector(0 to length - 1);
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  begin
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    for index in result'reverse_range loop
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      result(index) := digit( temp rem 2 );
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      temp := temp / 2;
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    end loop;
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    return result;
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  end function natural_to_bv;
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  procedure all_possible_values ( signal bv : out bit_vector;
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				  delay_between_values : in delay_length ) is
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  begin
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    bv <= natural_to_bv(0, bv'length);
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    for value in 1 to 2**bv'length - 1 loop
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      wait for delay_between_values;
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      bv <= natural_to_bv(value, bv'length);
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    end loop;
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  end procedure all_possible_values;
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  procedure all_possible_values ( signal bv : out std_ulogic_vector;
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				  delay_between_values : in delay_length ) is
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  begin
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    bv <= To_StdULogicVector(natural_to_bv(0, bv'length));
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    for value in 1 to 2**bv'length - 1 loop
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      wait for delay_between_values;
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      bv <= To_StdULogicVector(natural_to_bv(value, bv'length));
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    end loop;
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  end procedure all_possible_values;
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  procedure all_possible_values ( signal bv : out std_logic_vector;
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				  delay_between_values : in delay_length ) is
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  begin
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    bv <= To_StdLogicVector(natural_to_bv(0, bv'length));
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    for value in 1 to 2**bv'length - 1 loop
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      wait for delay_between_values;
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      bv <= To_StdLogicVector(natural_to_bv(value, bv'length));
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    end loop;
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  end procedure all_possible_values;
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end package body stimulus_generators;
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