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1
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2
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ap_a_ap_a_02.vhd
3
ERROR: Parse error at line 42 column 8:
4

    
5
32: library ieee;  use ieee.std_logic_1164.all;
6
33: 
7
34: architecture test of ap_a_02 is
8
35: 
9
36:   -- code from book
10
37: 
11
38:   -- end code from book
12
39: 
13
40: begin
14
41: 
15
42:   b1 : block is
16
           ^
17
43:                signal sulv : std_ulogic_vector(7 downto 0);
18
44:              signal slv : std_logic_vector(7 downto 0);
19
45:   begin
20
46:     -- code from book
21
47: 
22
48:     sulv <= To_stdulogicvector ( slv );
23
49: 
24
50:     -- end code from book
25
51:     slv <= "10101010";
26
52:   end block b1;
27

    
28
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ap_a_ap_a_03.vhd
29
ERROR: Parse error at line 38 column 8:
30

    
31
28: 
32
29: end entity ap_a_03;
33
30: 
34
31: 
35
32: library ieee;  use ieee.std_logic_1164.all;
36
33: use ieee.numeric_std.all;
37
34: 
38
35: architecture test of ap_a_03 is
39
36: begin
40
37: 
41
38:   b1 : block is
42
           ^
43
39:                -- code from book
44
40: 
45
41:                type unsigned is array ( natural range <> ) of std_logic;
46
42:              type signed is array ( natural range <> ) of std_logic;
47
43: 
48
44:              -- end code from book
49
45:   begin
50
46:   end block b1;
51
47: 
52
48: 
53

    
54
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ap_a_ap_a_09.vhd
55
ERROR: Parse error at line 40 column 8:
56

    
57
30: 
58
31: 
59
32: library ieee;  use ieee.std_logic_1164.all;
60
33: 
61
34: architecture test of ap_a_09 is
62
35: 
63
36:   signal a, b, c, d : integer := 0;
64
37: 
65
38: begin
66
39: 
67
40:   b1 : block is
68
           ^
69
41:                signal y : integer;
70
42:   begin
71
43:     -- code from book
72
44: 
73
45:     y <= a + b + c + d;
74
46: 
75
47:     -- end code from book
76
48:   end block b1;
77
49: 
78
50:   b2 : block is
79

    
80
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ap_a_ap_a_10.vhd
81
ERROR: Parse error at line 43 column 8:
82

    
83
33: library stimulus;  
84
34: use stimulus.stimulus_generators.all;
85
35: 
86
36: architecture test of ap_a_10 is
87
37: 
88
38:   signal a, b, c, d : std_ulogic;
89
39:   signal test_vector : std_ulogic_vector(1 to 4);
90
40: 
91
41: begin
92
42: 
93
43:   b1 : block is
94
           ^
95
44:                signal y : std_ulogic;
96
45:   begin
97
46:     -- code from book
98
47: 
99
48:     y <= a or b or c or d;
100
49: 
101
50:     -- end code from book
102
51:   end block b1;
103
52: 
104
53:   b2 : block is
105

    
106
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ap_a_fg_a_01.vhd
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ERROR: Parse error at line 51 column 8:
108

    
109
41:   begin
110
42:     clk <= '0';  d <= '0';  wait for 10 ns;
111
43:     clk <= '1', '0' after 10 ns;  wait for 20 ns;
112
44:     d <= '1';  wait for 10 ns;
113
45:     clk <= '1', '0' after 20 ns;  d <= '0' after 10 ns;
114
46: 
115
47:     wait;
116
48:   end process stimulus;
117
49: 
118
50: 
119
51:   b1 : block is
120
           ^
121
52:                signal q : std_ulogic;
122
53:   begin
123
54: 
124
55:     -- code from book
125
56: 
126
57:     process (clk) is
127
58:     begin
128
59:       if rising_edge(clk) then
129
60:         q <= d;
130
61:       end if;
131

    
132
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ap_a_fg_a_02.vhd
133
ERROR: Parse error at line 51 column 8:
134

    
135
41:   begin
136
42:     clk <= '0';  a <= '0';  b <= '0';  wait for 10 ns;
137
43:     clk <= '1', '0' after 10 ns;  wait for 20 ns;
138
44:     b <= '1';  wait for 10 ns;
139
45:     clk <= '1', '0' after 20 ns;  a <= '0' after 10 ns;
140
46: 
141
47:     wait;
142
48:   end process stimulus;
143
49: 
144
50: 
145
51:   b1 : block is
146
           ^
147
52:                signal q : std_ulogic;
148
53:   begin
149
54: 
150
55:     -- code from book
151
56: 
152
57:     process (clk) is
153
58:                     variable d : std_ulogic;
154
59:     begin
155
60:       if a = b then
156
61:         d := '1';
157

    
158
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ap_a_fg_a_03.vhd
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ERROR: Parse error at line 59 column 43:
160

    
161
49: 
162
50: -- end code from book
163
51: 
164
52: 
165
53: 
166
54:                entity fg_a_03 is
167
55:                end entity fg_a_03;
168
56: 
169
57: 
170
58:                library ieee;
171
59:                use ieee.std_logic_1164.all, ieee.numeric_std.all;
172
                                              ^
173
60: 
174
61:                architecture test of fg_a_03 is
175
62: 
176
63:                  signal a, b, c, y : natural := 0;
177
64:                  signal ovf : std_ulogic;
178
65: 
179
66:                begin
180
67: 
181
68:                  dut : entity work.add_and_sub
182
69:                    port map ( a, b, c, y, ovf );
183

    
184
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ap_a_fg_a_11.vhd
185
ERROR: Parse error at line 30 column 25:
186

    
187
20: -- ---------------------------------------------------------------------
188
21: --
189
22: -- $Id: ap_a_fg_a_11.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
190
23: -- $Revision: 1.2 $
191
24: --
192
25: -- ---------------------------------------------------------------------
193
26: 
194
27: library ieee;  use ieee.std_logic_1164.all;
195
28: 
196
29:                entity RAM16x1 is
197
30:                  port ( \a<0>\, \a<1>\, \a<2>\, \a<3>\ : in std_ulogic;
198
                            ^
199
31:                         \d\, \we\ : in std_ulogic;
200
32:                         \o\ : out std_ulogic );
201
33:                end entity RAM16x1;
202
34: 
203
35: 
204
36:                architecture a of RAM16x1 is
205
37:                begin
206
38:                end architecture a;
207
39: 
208
40: 
209

    
210
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/bv_arithmetic_body.vhd
211
ERROR: Parse error at line 143 column 16:
212

    
213
133:   function "+" ( bv1, bv2 : in bit_vector ) return bit_vector is
214
134: 
215
135:     alias op1 : bit_vector(bv1'length - 1 downto 0) is bv1;
216
136:     alias op2 : bit_vector(bv2'length - 1 downto 0) is bv2;  
217
137:     variable result : bit_vector(bv1'length - 1 downto 0);
218
138:     variable carry_in : bit;
219
139:     variable carry_out : bit := '0';
220
140: 
221
141:   begin
222
142:     if bv1'length /= bv2'length then
223
143:       report """+"": operands of different lengths"
224
                    ^
225
144:         severity failure;
226
145:     else
227
146:       for index in result'reverse_range loop
228
147:         carry_in := carry_out;  -- of previous bit
229
148:         result(index) := op1(index) xor op2(index) xor carry_in;
230
149:         carry_out := (op1(index) and op2(index))
231
150:                      or (carry_in and (op1(index) xor op2(index)));
232
151:       end loop;
233
152:     end if;
234
153:     return result;
235

    
236
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/bv_images_body.vhd
237
ERROR: Parse error at line 51 column 18:
238

    
239
41:   -- (in the format B"...")
240
42:   -- Length of result is bv'length + 3
241
43: 
242
44:   function image (bv : in bit_vector) return string is
243
45: 
244
46:     alias bv_norm : bit_vector(1 to bv'length) is bv;
245
47:     variable result : string(1 to bv'length + 3);
246
48: 
247
49:   begin
248
50:     result(1) := 'B';
249
51:     result(2) := '"';
250
                     ^
251
52:     for index in bv_norm'range loop
252
53:       if bv_norm(index) = '0' then
253
54:         result(index + 2) := '0';
254
55:       else
255
56:         result(index + 2) := '1';
256
57:       end if;
257
58:     end loop;
258
59:     result(bv'length + 3) := '"';
259
60:     return result;
260
61:   end image;
261

    
262
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_01_tb_01_01.vhd
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ERROR: Parse error at line 44 column 5:
264

    
265
34: 
266
35: begin
267
36: 
268
37:   dut : entity work.reg4(behav)
269
38:     port map ( d0 => d0, d1 => d1, d2 => d2, d3 => d3, en => en, clk => clk,
270
39:                q0 => q0, q1 => q1, q2 => q2, q3 => q3 );
271
40: 
272
41:   stimulus : process is
273
42:   begin
274
43:     wait for 20 ns;
275
44:     (d0, d1, d2, d3) <= bit_vector'("1010"); wait for 20 ns;
276
        ^
277
45:     en <= '1';     wait for 20 ns;
278
46:     clk <= '1';     wait for 20 ns;
279
47:     (d0, d1, d2, d3) <= bit_vector'("0101"); wait for 20 ns;
280
48:     clk <= '0';     wait for 20 ns;
281
49:     (d0, d1, d2, d3) <= bit_vector'("0000"); wait for 20 ns;
282
50:     en <= '1';     wait for 20 ns;
283
51:     (d0, d1, d2, d3) <= bit_vector'("1111"); wait for 20 ns;
284
52: 
285
53:     wait;
286
54:   end process stimulus;
287

    
288
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_01_tb_01_02.vhd
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ERROR: Parse error at line 44 column 5:
290

    
291
34: 
292
35: begin
293
36: 
294
37:   dut : entity work.reg4(struct)
295
38:     port map ( d0 => d0, d1 => d1, d2 => d2, d3 => d3, en => en, clk => clk,
296
39:                q0 => q0, q1 => q1, q2 => q2, q3 => q3 );
297
40: 
298
41:   stimulus : process is
299
42:   begin
300
43:     wait for 20 ns;
301
44:     (d0, d1, d2, d3) <= bit_vector'("1010"); wait for 20 ns;
302
        ^
303
45:     en <= '1';     wait for 20 ns;
304
46:     clk <= '1';     wait for 20 ns;
305
47:     (d0, d1, d2, d3) <= bit_vector'("0101"); wait for 20 ns;
306
48:     clk <= '0';     wait for 20 ns;
307
49:     (d0, d1, d2, d3) <= bit_vector'("0000"); wait for 20 ns;
308
50:     en <= '1';     wait for 20 ns;
309
51:     (d0, d1, d2, d3) <= bit_vector'("1111"); wait for 20 ns;
310
52: 
311
53:     wait;
312
54:   end process stimulus;
313

    
314
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_03_ch_03_12.vhd
315
ERROR: Parse error at line 102 column 7:
316

    
317
 92:       -- . . .
318
 93:     end loop outer;
319
 94:     -- . . .                        -- target B
320
 95: 
321
 96:     --
322
 97: 
323
 98:     -- "statement..." in roman italic with hyphens
324
 99: 
325
100:     loop
326
101:       -- statement_1;
327
102:       next when condition;
328
           ^
329
103:       -- statement_2;
330
104:     end loop;
331
105: 
332
106:     --
333
107: 
334
108:     -- "statement..." in roman italic with hyphens
335
109: 
336
110:     loop
337
111:       -- statement_1;
338
112:       if not condition then
339

    
340
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_03_tb_03_02.vhd
341
ERROR: Parse error at line 33 column 33:
342

    
343
23: -- $Revision: 1.1.1.1 $
344
24: --
345
25: -- ---------------------------------------------------------------------
346
26: 
347
27: package test_bench_03_02 is
348
28: 
349
29:   -- following type used in Figure 3-02
350
30: 
351
31:   -- code from book:
352
32: 
353
33:   type sel_range is range 0 to 3;
354
                                    ^
355
34: 
356
35:   -- end of code from book
357
36: 
358
37: end package test_bench_03_02;
359
38: 
360

    
361
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_03_tb_03_03.vhd
362
ERROR: Parse error at line 35 column 20:
363

    
364
25: -- ---------------------------------------------------------------------
365
26: 
366
27: entity test_bench_03_03 is
367
28: end entity test_bench_03_03;
368
29: 
369
30: library ieee;  
370
31: use ieee.std_logic_1164.all;
371
32: 
372
33: architecture test_mux4_demo of test_bench_03_03 is
373
34: 
374
35:   signal sel : work.test_bench_03_02.sel_range := 0;
375
                       ^
376
36:   signal d0, d1, d2, d3, z : std_ulogic;
377
37: 
378
38: begin
379
39: 
380
40:   dut : entity work.mux4(demo)
381
41:     port map ( sel => sel,
382
42:                d0 => d0, d1 => d1, d2 => d2, d3 => d3,
383
43:                z => z );
384
44: 
385
45:   stimulus : process is
386

    
387
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_04_ch_04_01.vhd
388
ERROR: Parse error at line 39 column 18:
389

    
390
29: end entity ch_04_01;
391
30: 
392
31: 
393
32: ----------------------------------------------------------------
394
33: 
395
34: 
396
35: architecture test of ch_04_01 is
397
36: begin
398
37: 
399
38: 
400
39:   block_04_1_a : block is
401
                     ^
402
40: 
403
41:                          -- code from book:
404
42: 
405
43:                          type word is array (0 to 31) of bit;
406
44: 
407
45:                        --
408
46: 
409
47:                        type controller_state is (initial, idle, active, error);
410
48: 
411
49:                        type state_counts is array (idle to error) of natural;
412

    
413
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_04_ch_04_02.vhd
414
ERROR: Parse error at line 44 column 54:
415

    
416
34: 
417
35: architecture test of ch_04_02 is
418
36: begin
419
37: 
420
38: 
421
39:   process_04_1_b : process is
422
40: 
423
41:                              -- code from book:
424
42: 
425
43:                              type symbol is ('a', 't', 'd', 'h', digit, cr, error);
426
44:                            type state is range 0 to 6;
427
                                                         ^
428
45: 
429
46:                            type transition_matrix is array (state, symbol) of state;
430
47: 
431
48:                            variable transition_table : transition_matrix;
432
49: 
433
50:                            -- end of code from book
434
51: 
435
52:                            variable next_state : state;
436
53: 
437
54:                            -- code from book:
438

    
439
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_04_ch_04_10.vhd
440
ERROR: Parse error at line 86 column 60:
441

    
442
76: 
443
77:     -- end of code from book
444
78: 
445
79:     wait;
446
80:   end process process_04_4_a;
447
81: 
448
82: 
449
83:   process_04_4_b : process is
450
84: 
451
85:                              type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, nop);
452
86:                            type reg_number is range 0 to 31;
453
                                                               ^
454
87: 
455
88:                            type instruction is record
456
89:                                                  opcode : opcodes;
457
90:                                                  source_reg1, source_reg2, dest_reg : reg_number;
458
91:                                                  displacement : integer;
459
92:                                                end record instruction;
460
93: 
461
94:                            -- code from book:
462
95: 
463
96:                            constant midday : time_stamp := (hours => 12, minutes => 0, seconds => 0);
464

    
465
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_04_fg_04_03.vhd
466
ERROR: Parse error at line 44 column 56:
467

    
468
34: 
469
35: architecture test of fg_04_03 is
470
36: begin
471
37: 
472
38:   -- code from book:
473
39: 
474
40:   modem_controller : process is
475
41: 
476
42:                                type symbol is ('a', 't', 'd', 'h', digit, cr, other);
477
43:                              type symbol_string is array (1 to 20) of symbol;
478
44:                              type state is range 0 to 6;
479
                                                           ^
480
45:                              type transition_matrix is array (state, symbol) of state;
481
46: 
482
47:                              constant next_state : transition_matrix :=
483
48:                                ( 0 => ('a' => 1, others => 6),
484
49:                                  1 => ('t' => 2, others => 6),
485
50:                                  2 => ('d' => 3, 'h' => 5, others => 6),
486
51:                                  3 => (digit => 4, others => 6),
487
52:                                  4 => (digit => 4, cr => 0, others => 6),
488
53:                                  5 => (cr => 0, others => 6),
489
54:                                  6 => (cr => 0, others => 6) );
490

    
491
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_04_fg_04_06.vhd
492
ERROR: Parse error at line 33 column 35:
493

    
494
23: -- $Revision: 1.2 $
495
24: --
496
25: -- ---------------------------------------------------------------------
497
26: 
498
27: architecture system_level of computer is
499
28: 
500
29:   type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, -- . . .);
501
30:                    -- not in book:
502
31:                    nop);
503
32:   -- end not in book
504
33:   type reg_number is range 0 to 31;
505
                                      ^
506
34:   constant r0 : reg_number := 0;  constant r1 : reg_number := 1;  -- . . .
507
35:   -- not in book:
508
36:   constant r2 : reg_number := 2;
509
37:   -- end not in book
510
38: 
511
39:   type instruction is record
512
40:                         opcode : opcodes;
513
41:                         source_reg1, source_reg2, dest_reg : reg_number;
514
42:                         displacement : integer;
515
43:                       end record instruction;
516

    
517
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_05_ch_05_07.vhd
518
ERROR: Parse error at line 72 column 43:
519

    
520
62: 
521
63: 
522
64:   ----------------
523
65: 
524
66: 
525
67:   process_05_3_d : process (clk, d) is
526
68:   begin
527
69: 
528
70:     -- code from book:
529
71: 
530
72:     assert (not clk'event) or clk'delayed'last_event >= Tpw_clk
531
                                              ^
532
73:       report "Clock frequency too high";
533
74: 
534
75:     -- end of code from book
535
76: 
536
77:   end process process_05_3_d;
537
78: 
538
79: 
539
80:   ----------------
540
81: 
541
82: 
542

    
543
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_05_ch_05_08.vhd
544
ERROR: Parse error at line 44 column 18:
545

    
546
34: 
547
35:   constant T_pd : delay_length := 5 ns;
548
36: 
549
37:   signal a, b : bit := '0';
550
38:   signal test_inputs : bit_vector(1 to 2);
551
39: 
552
40:   use stimulus.stimulus_generators.all;
553
41: 
554
42: begin
555
43: 
556
44:   block_05_3_f : block is
557
                     ^
558
45: 
559
46:                          signal sum, carry : bit;
560
47: 
561
48:   begin
562
49: 
563
50:     -- code from book:
564
51: 
565
52:     half_add : process is
566
53:     begin
567
54:       sum <= a xor b after T_pd;
568

    
569
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_05_ch_05_14.vhd
570
ERROR: Parse error at line 42 column 18:
571

    
572
32: ----------------------------------------------------------------
573
33: 
574
34: 
575
35: architecture test of ch_05_14 is
576
36: 
577
37:   signal PC, functional_next_PC, equivalent_next_PC : integer := 0;
578
38: 
579
39: begin
580
40: 
581
41: 
582
42:   block_05_3_p : block is
583
                     ^
584
43:                          port ( next_PC : out integer );
585
44:                        port map ( next_PC => functional_next_PC );
586
45:   begin
587
46: 
588
47:     -- code from book:
589
48: 
590
49:     PC_incr : next_PC <= PC + 4 after 5 ns;
591
50: 
592
51:     -- end of code from book
593
52: 
594

    
595
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_05_ch_05_15.vhd
596
ERROR: Parse error at line 42 column 18:
597

    
598
32: ----------------------------------------------------------------
599
33: 
600
34: 
601
35: architecture test of ch_05_15 is
602
36: 
603
37:   signal functional_reset, equivalent_reset : bit := '0';
604
38: 
605
39: begin
606
40: 
607
41: 
608
42:   block_05_3_r : block is
609
                     ^
610
43:                          port ( reset : out bit );
611
44:                        port map ( reset => functional_reset );
612
45:   begin
613
46: 
614
47:     -- code from book:
615
48: 
616
49:     reset_gen : reset <= '1', '0' after 200 ns when extended_reset else
617
50:                          '1', '0' after 50 ns;
618
51: 
619
52:     -- end of code from book
620

    
621
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_05_ch_05_18.vhd
622
ERROR: Parse error at line 63 column 18:
623

    
624
53: ----------------------------------------------------------------
625
54: 
626
55: 
627
56: architecture test of ch_05_18 is
628
57: 
629
58: 
630
59: 
631
60: begin
632
61: 
633
62: 
634
63:   block_05_4_a : block is
635
                     ^
636
64:                          signal cpu_rd, cpu_wr, cpu_mem,
637
65:                        mem_ras, mem_cas, mem_we, cpu_rdy : bit;
638
66:   begin
639
67: 
640
68:     -- code from book:
641
69: 
642
70:     main_mem_controller : entity work.DRAM_controller(fpld)
643
71:       port map ( cpu_rd, cpu_wr, cpu_mem,
644
72:                  mem_ras, mem_cas, mem_we, cpu_rdy );
645
73: 
646

    
647
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_05_ch_05_21.vhd
648
ERROR: Parse error at line 82 column 66:
649

    
650
72: 
651
73:   serial_write_gate : entity work.and_gate
652
74:     port map ( i(1) => serial_select,
653
75:                i(2) => write_en,
654
76:                i(3) => bus_clk,
655
77:                y => serial_wr );
656
78: 
657
79:   -- end of code from book
658
80: 
659
81:   stimulus_proc : all_possible_values( bv => test_input,
660
82:                                   delay_between_values => 10 ns );
661
                                                                     ^
662
83: 
663
84:   (serial_select, write_en, bus_clk) <= test_input;
664
85: 
665
86: end architecture test;
666
87: 
667

    
668
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_05_ch_05_23.vhd
669
ERROR: Parse error at line 66 column 38:
670

    
671
56: begin
672
57: 
673
58:   -- code from book:
674
59: 
675
60:   f_cell : entity work.and_or_inv
676
61:     port map (a1 => A, a2 => B, b1 => C, b2 => open, y => F);
677
62: 
678
63:   -- end of code from book
679
64: 
680
65:   stimulus_proc : all_possible_values( bv => test_input,
681
66:       delay_between_values => 10 ns );
682
                                         ^
683
67: 
684
68:   (A, B, C) <= test_input;
685
69: 
686
70:   verifier :
687
71:     postponed assert F = not ((A and B) or C)
688
72:       report "function model produced unexpected result";
689
73: 
690
74: end architecture test;
691
75: 
692

    
693
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_05_ch_05_24.vhd
694
ERROR: Parse error at line 63 column 18:
695

    
696
53: architecture test of ch_05_24 is
697
54: 
698
55:   signal s1, s2, ctrl1_a, ctrl1_b : bit;
699
56:   signal test_input : bit_vector(1 to 2);
700
57: 
701
58:   use stimulus.stimulus_generators.all;
702
59: 
703
60: begin
704
61: 
705
62: 
706
63:   block_05_4_a : block is
707
                     ^
708
64:                          port ( ctrl1 : out bit );
709
65:                        port map ( ctrl1 => ctrl1_a );
710
66:   begin
711
67: 
712
68:     -- code from book:
713
69: 
714
70:     g1 : entity work.and3 port map (a => s1, b => s2, not_z => ctrl1);
715
71: 
716
72:     -- end of code from book
717
73: 
718

    
719
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_05_fg_05_04.vhd
720
ERROR: Parse error at line 67 column 7:
721

    
722
57:                        := ( "0000",
723
58:                             "0010",
724
59:                             "0100",
725
60:                             "0111",
726
61:                             "1001",
727
62:                             "1010",
728
63:                             "1101",
729
64:                             "1111" );
730
65:   begin
731
66:     for i in stim_vector'range loop
732
67:       (a, b, sel) <= stim_vector(i)(0 to 2);
733
          ^
734
68:       wait for 10 ns;
735
69:       assert z = stim_vector(i)(3);
736
70:     end loop;
737
71:     wait;
738
72:   end process stimulus;
739
73: 
740
74: 
741
75: end architecture test;
742
76: 
743

    
744
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_05_fg_05_17.vhd
745
ERROR: Parse error at line 41 column 20:
746

    
747
31: 
748
32: architecture test of fg_05_17 is
749
33: 
750
34:   use stimulus.stimulus_generators.all;
751
35: 
752
36:   signal sel0, sel1, d0, d1, d2, d3 : bit := '0';
753
37:   signal functional_z, equivalent_z : bit;
754
38: 
755
39: begin
756
40: 
757
41:   functional_mux : block is
758
                       ^
759
42:                            port ( z : out bit );
760
43:                          port map ( z => functional_z );
761
44:   begin
762
45: 
763
46:     -- code from book
764
47: 
765
48:     zmux : z <= d0 when sel1 = '0' and sel0 = '0' else
766
49:                 d1 when sel1 = '0' and sel0 = '1' else
767
50:                 d2 when sel1 = '1' and sel0 = '0' else
768
51:                 d3 when sel1 = '1' and sel0 = '1';
769

    
770
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_05_fg_05_19.vhd
771
ERROR: Parse error at line 47 column 26:
772

    
773
37: 
774
38:   signal first_priority_request,
775
39:     first_normal_request,
776
40:     reset_request : request_type := 0;
777
41:   signal functional_request, equivalent_request : request_type;
778
42:   signal priority_waiting : boolean := false;
779
43:   signal server_status : server_status_type := busy;
780
44: 
781
45: begin
782
46: 
783
47:   functional_scheduler : block is
784
                             ^
785
48:                                  port ( request : out request_type );
786
49:                                port map ( request => functional_request );
787
50:   begin
788
51: 
789
52:     -- code from book
790
53: 
791
54:     scheduler :
792
55:       request <= first_priority_request after scheduling_delay
793
56:                  when priority_waiting and server_status = ready else
794
57:                  first_normal_request after scheduling_delay
795

    
796
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_05_fg_05_21.vhd
797
ERROR: Parse error at line 35 column 5:
798

    
799
25: -- ---------------------------------------------------------------------
800
26: 
801
27: entity full_adder is
802
28:   port ( a, b, c_in : bit;  s, c_out : out bit );
803
29: end entity full_adder;
804
30: 
805
31: architecture truth_table of full_adder is
806
32: begin
807
33: 
808
34:   with bit_vector'(a, b, c_in) select
809
35:     (c_out, s) <= bit_vector'("00") when "000",
810
        ^
811
36:     bit_vector'("01") when "001",
812
37:     bit_vector'("01") when "010",
813
38:     bit_vector'("10") when "011",
814
39:     bit_vector'("01") when "100",
815
40:     bit_vector'("10") when "101",
816
41:     bit_vector'("10") when "110",
817
42:     bit_vector'("11") when "111";
818
43: 
819
44: end architecture truth_table;
820
45: 
821

    
822
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_05_fg_05_23.vhd
823
ERROR: Parse error at line 32 column 11:
824

    
825
22: -- $Id: ch_05_fg_05_23.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
826
23: -- $Revision: 1.2 $
827
24: --
828
25: -- ---------------------------------------------------------------------
829
26: 
830
27: entity S_R_flipflop is
831
28:   port ( s, r : in bit;  q, q_n : out bit );
832
29: 
833
30: begin
834
31: 
835
32:   check : assert not (s = '1' and r = '1')
836
              ^
837
33:     report "Incorrect use of S_R_flip_flop: s and r both '1'";
838
34: 
839
35: end entity S_R_flipflop;
840
36: 
841

    
842
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_05_tb_05_02.vhd
843
ERROR: Parse error at line 63 column 7:
844

    
845
53:                             "1000",
846
54:                             "1001",
847
55:                             "1010",
848
56:                             "1011",
849
57:                             "1100",
850
58:                             "1101",
851
59:                             "1110",
852
60:                             "1111" );
853
61:   begin
854
62:     for i in stim_vector'range loop
855
63:       (a1, a2, b1, b2) <= stim_vector(i);
856
          ^
857
64:       wait for 10 ns;
858
65:       assert y = not ( (stim_vector(i)(0) and stim_vector(i)(1))
859
66:                 or (stim_vector(i)(2) and stim_vector(i)(3)) );
860
67:     end loop;
861
68:     wait;
862
69:   end process stimulus;
863
70: 
864
71: end architecture test;
865
72: 
866

    
867
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_05_tb_05_04.vhd
868
ERROR: Parse error at line 53 column 7:
869

    
870
43:                        := ( "0000",
871
44:                             "0100",
872
45:                             "1001",
873
46:                             "1101",
874
47:                             "0010",
875
48:                             "0111",
876
49:                             "1010",
877
50:                             "1111" );
878
51:   begin
879
52:     for i in stim_vector'range loop
880
53:       (a, b, sel) <= stim_vector(i)(0 to 2);
881
          ^
882
54:       wait for 10 ns;
883
55:       assert z = stim_vector(i)(3);
884
56:     end loop;
885
57:     wait;
886
58:   end process stimulus;
887
59: 
888
60: 
889
61: end architecture test;
890
62: 
891

    
892
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_05_tb_05_09.vhd
893
ERROR: Parse error at line 45 column 5:
894

    
895
35: 
896
36: begin
897
37: 
898
38:   dut : entity work.reg4(struct)
899
39:     port map ( clk => clk, clr => clr,
900
40:         d0 => d0, d1 => d1, d2 => d2, d3 => d3,
901
41:         q0 => q0, q1 => q1, q2 => q2, q3 => q3 );
902
42: 
903
43:   stimulus : process is
904
44:   begin
905
45:     (d3, d2, d1, d0) <= bit_vector'(b"1010"); wait for 10 ns;
906
        ^
907
46:     clk <= '1';     wait for 10 ns;
908
47:     (d3, d2, d1, d0) <= bit_vector'(b"0101"); wait for 10 ns;
909
48:     clk <= '0';     wait for 10 ns;
910
49:     (d3, d2, d1, d0) <= bit_vector'(b"1111"); wait for 10 ns;
911
50:     clr <= '1';     wait for 10 ns;
912
51:     clk <= '1';     wait for 10 ns;
913
52:     clr <= '0';     wait for 10 ns;
914
53:     clk <= '0';     wait for 10 ns;
915
54: 
916
55:     wait;
917

    
918
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_07_ch_07_02.vhd
919
ERROR: Parse error at line 47 column 18:
920

    
921
37:   constant val1 : integer := 1;
922
38: 
923
39:   procedure p ( signal s1, s2 : in bit;  val1 : in integer ) is
924
40:   begin
925
41:     null;
926
42:   end procedure p;
927
43: 
928
44: begin
929
45: 
930
46: 
931
47:   block_07_3_a : block is
932
                     ^
933
48: 
934
49:                          signal s1, s2 : bit;
935
50: 
936
51:   begin
937
52: 
938
53:     -- code from book:
939
54: 
940
55:     call_proc : p ( s1, s2, val1 );
941
56: 
942
57:     -- end of code from book
943

    
944
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_07_ch_07_06.vhd
945
ERROR: Parse error at line 44 column 26:
946

    
947
34: begin
948
35: 
949
36:   process_07_5_b : process is
950
37: 
951
38:                              -- code from book:
952
39: 
953
40:                              function "+" ( left, right : in bit_vector ) return bit_vector is
954
41:   begin
955
42:     -- . . .
956
43:     -- not in book
957
44:     return bv_arithmetic."+"(left, right);
958
                             ^
959
45:     -- end not in book
960
46:   end function "+";
961
47: 
962
48:   variable addr_reg : bit_vector(31 downto 0);
963
49:   -- . . .
964
50: 
965
51:   -- end of code from book
966
52: 
967
53:   -- code from book:
968
54: 
969

    
970
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_07_fg_07_05.vhd
971
ERROR: Parse error at line 57 column 47:
972

    
973
47:                                       variable mem_address_reg, mem_data_reg : word;
974
48:                                     -- end not in book
975
49: 
976
50:                                     procedure read_memory is
977
51:                                     begin
978
52:                                       address_bus <= mem_address_reg;
979
53:                                       mem_read <= '1';
980
54:                                       mem_request <= '1';
981
55:                                       wait until mem_ready = '1' or reset = '1';
982
56:                                       if reset = '1' then
983
57:                                         return;
984
                                                  ^
985
58:                                       end if;
986
59:                                       mem_data_reg := data_bus_in;
987
60:                                       mem_request <= '0';
988
61:                                       wait until mem_ready = '0';
989
62:                                     end procedure read_memory;
990
63: 
991
64:   begin
992
65:     -- . . .    -- initialization
993
66:     -- not in book
994
67:     if reset = '1' then
995

    
996
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_07_fg_07_12.vhd
997
ERROR: Parse error at line 44 column 15:
998

    
999
34:   -- code from book
1000
35: 
1001
36:   procedure find_first_set ( v : in bit_vector;
1002
37:                              found : out boolean;
1003
38:                              first_set_index : out natural ) is
1004
39:   begin
1005
40:     for index in v'range loop
1006
41:       if v(index) = '1' then
1007
42:         found := true;
1008
43:         first_set_index := index;
1009
44:         return;
1010
                  ^
1011
45:       end if;
1012
46:     end loop;
1013
47:     found := false;
1014
48:   end procedure find_first_set;
1015
49: 
1016
50:   -- end code from book
1017
51: 
1018
52: begin
1019
53: 
1020
54:   stimulus : process is
1021

    
1022
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_07_fg_07_14.vhd
1023
ERROR: Parse error at line 55 column 57:
1024

    
1025
45:   -- end code from book
1026
46: 
1027
47:   signal ready, phi2 : bit := '0';
1028
48:   constant Tsu_rdy_clk : delay_length := 4 ns;
1029
49: 
1030
50: begin
1031
51: 
1032
52:   -- code from book (in text)
1033
53: 
1034
54:   check_ready_setup : check_setup ( data => ready, clock => phi2,
1035
55:                                     Tsu => Tsu_rdy_clk );
1036
                                                            ^
1037
56: 
1038
57:   -- end code from book
1039
58: 
1040
59:   clock_gen : phi2 <= '1' after 10 ns, '0' after 20 ns when phi2 = '0';
1041
60: 
1042
61:   stimulus : ready <= '1' after 4 ns,
1043
62:                       '0' after 56 ns,
1044
63:                       '1' after 87 ns,
1045
64:                       '0' after 130 ns;
1046
65: 
1047

    
1048
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_07_fg_07_15.vhd
1049
ERROR: Parse error at line 62 column 47:
1050

    
1051
52:   signal phi1, phi2 : std_ulogic := '0';
1052
53:   -- . . .
1053
54: 
1054
55:   -- end code from book
1055
56: 
1056
57: begin
1057
58: 
1058
59:   -- code from book (in text)
1059
60: 
1060
61:   gen_phi1 : generate_clock ( phi1, Tperiod => 50 ns, Tpulse => 20 ns,
1061
62:                               Tphase => 0 ns );
1062
                                                  ^
1063
63: 
1064
64:   gen_phi2 : generate_clock ( phi2, Tperiod => 50 ns, Tpulse => 20 ns,
1065
65:                               Tphase => 25 ns );
1066
66: 
1067
67:   -- end code from book
1068
68: 
1069
69: end architecture test;
1070
70: 
1071

    
1072
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_07_fg_07_20.vhd
1073
ERROR: Parse error at line 77 column 3:
1074

    
1075
67:   dut : entity work.reg_ctrl
1076
68:     port map ( reg_addr_decoded, rd, wr, io_en, cpu_clk, reg_rd, reg_wr );
1077
69: 
1078
70:   stimulus_proc : process is
1079
71:   begin
1080
72:     all_possible_values( bv => test_vector,
1081
73:                          delay_between_values => 10 ns );
1082
74:     wait;
1083
75:   end process stimulus_proc;
1084
76: 
1085
77:   (reg_addr_decoded, rd, wr, io_en, cpu_clk) <= test_vector;
1086
      ^
1087
78: 
1088
79: end architecture test;
1089
80: 
1090

    
1091
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_08_ch_08_01.vhd
1092
ERROR: Parse error at line 45 column 58:
1093

    
1094
35: library ieee;
1095
36: 
1096
37: architecture test of ch_08_01 is
1097
38: begin
1098
39: 
1099
40: 
1100
41:   process_08_1_a : process is
1101
42: 
1102
43:                              -- code from book:
1103
44: 
1104
45:                              variable stored_state : ieee.std_logic_1164.std_ulogic;
1105
                                                             ^
1106
46: 
1107
47:                            -- end of code from book
1108
48: 
1109
49:   begin
1110
50: 
1111
51:     wait;
1112
52:   end process process_08_1_a;
1113
53: 
1114
54: 
1115
55: end architecture test;
1116

    
1117
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_08_ch_08_03.vhd
1118
ERROR: Parse error at line 47 column 58:
1119

    
1120
37: architecture test of ch_08_03 is
1121
38: begin
1122
39: 
1123
40: 
1124
41:   process_08_3_a : process is
1125
42: 
1126
43:                              -- code from book:
1127
44: 
1128
45:                              use work.cpu_types;
1129
46: 
1130
47:                            variable data_word : cpu_types.word;
1131
                                                             ^
1132
48:                            variable next_address : cpu_types.address;
1133
49: 
1134
50:                            -- end of code from book
1135
51: 
1136
52:   begin
1137
53:     wait;
1138
54:   end process process_08_3_a;
1139
55: 
1140
56: 
1141
57:   ----------------
1142

    
1143
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_08_ch_08_05.vhd
1144
ERROR: Parse error at line 56 column 48:
1145

    
1146
46:                       process_08_4_a : process is
1147
47: 
1148
48:                                                  constant a : integer := 10;
1149
49:                                                constant b : integer := 20;
1150
50:                                                variable result : boolean;
1151
51: 
1152
52:                       begin
1153
53: 
1154
54:                         -- code from book:
1155
55: 
1156
56:                         result := std.standard."<" ( a, b );
1157
                                                   ^
1158
57: 
1159
58:                         -- end of code from book
1160
59: 
1161
60:                         wait;
1162
61:                       end process process_08_4_a;
1163
62: 
1164
63: 
1165
64:                     end architecture test;
1166
65: 
1167

    
1168
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_08_fg_08_01.vhd
1169
ERROR: Parse error at line 50 column 9:
1170

    
1171
40: end package cpu_types;
1172
41: 
1173
42: -- end code from book
1174
43: 
1175
44: 
1176
45: 
1177
46: package fg_08_01 is
1178
47: 
1179
48:   constant status :
1180
49:     -- code from book
1181
50:     work.cpu_types.status_value
1182
            ^
1183
51:     -- end code from book
1184
52:     :=
1185
53:     -- code from book
1186
54:     work.cpu_types.status_value'(work.cpu_types.fetch)
1187
55:     -- end code from book
1188
56:     ;
1189
57: 
1190
58: end package fg_08_01;
1191
59: 
1192

    
1193
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_08_fg_08_02.vhd
1194
ERROR: Parse error at line 28 column 24:
1195

    
1196
18: -- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
1197
19: 
1198
20: -- ---------------------------------------------------------------------
1199
21: --
1200
22: -- $Id: ch_08_fg_08_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
1201
23: -- $Revision: 1.2 $
1202
24: --
1203
25: -- ---------------------------------------------------------------------
1204
26: 
1205
27: entity address_decoder is
1206
28:   port ( addr : in work.cpu_types.address;
1207
                           ^
1208
29:          status : in work.cpu_types.status_value;
1209
30:          mem_sel, int_sel, io_sel : out bit );
1210
31: end entity address_decoder;
1211
32: 
1212
33: --------------------------------------------------
1213
34: 
1214
35: architecture functional of address_decoder is
1215
36: 
1216
37:   constant mem_low : work.cpu_types.address := X"000000";
1217
38:   constant mem_high : work.cpu_types.address := X"EFFFFF";
1218

    
1219
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_08_fg_08_04.vhd
1220
ERROR: Parse error at line 32 column 25:
1221

    
1222
22: -- $Id: ch_08_fg_08_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
1223
23: -- $Revision: 1.2 $
1224
24: --
1225
25: -- ---------------------------------------------------------------------
1226
26: 
1227
27: -- not in book
1228
28: 
1229
29: library ieee;  use ieee.std_logic_1164.all;
1230
30: 
1231
31:                entity phase_locked_clock_gen is
1232
32:                  port ( reference : in std_ulogic;
1233
                            ^
1234
33:                         phi1, phi2 : out std_ulogic );
1235
34:                end entity phase_locked_clock_gen;
1236
35: 
1237
36: 
1238
37:                architecture std_cell of phase_locked_clock_gen is
1239
38: 
1240
39:                  --use work.clock_pkg.Tpw;
1241
40:                  use work.clock_pkg.all;
1242
41: 
1243
42:                begin
1244

    
1245
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_08_fg_08_07.vhd
1246
ERROR: Parse error at line 42 column 52:
1247

    
1248
32: -- end not in book
1249
33: 
1250
34: 
1251
35: 
1252
36: 
1253
37: architecture behavioral of cpu is
1254
38: begin
1255
39: 
1256
40:   interpreter : process is
1257
41: 
1258
42:                           variable instr_reg : work.cpu_types.word;
1259
                                                       ^
1260
43:                         variable instr_opcode : work.cpu_types.opcode;
1261
44: 
1262
45:   begin
1263
46:     -- . . .    -- initialize
1264
47:     loop
1265
48:       -- . . .    -- fetch instruction
1266
49:       instr_opcode := work.cpu_types.extract_opcode ( instr_reg );
1267
50:       case instr_opcode is
1268
51:         when work.cpu_types.op_nop => null;
1269
52:         when work.cpu_types.op_breq => -- . . .
1270

    
1271
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_08_fg_08_08.vhd
1272
ERROR: Parse error at line 49 column 26:
1273

    
1274
39: -- not in book
1275
40: library bv_utilities;
1276
41: use bv_utilities.bv_arithmetic;
1277
42: -- end not in book
1278
43: 
1279
44: package body bit_vector_signed_arithmetic is
1280
45: 
1281
46:   function "+" ( bv1, bv2 : bit_vector ) return bit_vector is -- . . .
1282
47:     -- not in book
1283
48:   begin
1284
49:     return bv_arithmetic."+"(bv1, bv2);
1285
                             ^
1286
50:   end function "+";
1287
51:   -- end not in book
1288
52: 
1289
53:   function "-" ( bv : bit_vector ) return bit_vector is -- . . .
1290
54:     -- not in book
1291
55:   begin
1292
56:     return bv_arithmetic."-"(bv);
1293
57:   end function "-";
1294
58:   -- end not in book
1295
59: 
1296

    
1297
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_08_fg_08_10.vhd
1298
ERROR: Parse error at line 42 column 25:
1299

    
1300
32: architecture test of fg_08_10 is
1301
33: 
1302
34:   -- code from book
1303
35: 
1304
36:   function "<" ( a, b : bit_vector ) return boolean is
1305
37:     variable tmp1 : bit_vector(a'range) := a;
1306
38:     variable tmp2 : bit_vector(b'range) := b;
1307
39:   begin
1308
40:     tmp1(tmp1'left) := not tmp1(tmp1'left);
1309
41:     tmp2(tmp2'left) := not tmp2(tmp2'left);
1310
42:     return std.standard."<" ( tmp1, tmp2 );
1311
                            ^
1312
43:   end function "<";
1313
44: 
1314
45:   -- end code from book
1315
46: 
1316
47:   signal a, b : bit_vector(7 downto 0);
1317
48:   signal result : boolean;
1318
49: 
1319
50: begin
1320
51: 
1321
52:   dut : result <= a < b;
1322

    
1323
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_09_ch_09_01.vhd
1324
ERROR: Parse error at line 64 column 109:
1325

    
1326
54:                            -- alias PSW is CPU_registers.program_status;
1327
55:                            -- alias PC is CPU_registers.program_counter;
1328
56:                            -- alias GPR is CPU_registers.general_purpose_registers;
1329
57: 
1330
58:                            alias PSW : bit_vector(31 downto 0) is CPU_registers.program_status;
1331
59:                            alias PC : bit_vector(31 downto 0) is CPU_registers.program_counter;
1332
60:                            alias GPR : register_array is CPU_registers.general_purpose_registers;
1333
61: 
1334
62:                            -- alias SP is CPU_registers.general_purpose_registers(15);
1335
63: 
1336
64:                            alias SP : bit_vector(31 downto 0) is CPU_registers.general_purpose_registers(15);
1337
                                                                                                                ^
1338
65: 
1339
66:                            -- alias interrupt_level is PSW(30 downto 26);
1340
67: 
1341
68:                            alias interrupt_level : bit_vector(30 downto 26) is PSW(30 downto 26);
1342
69: 
1343
70:                            -- end revision
1344
71: 
1345
72:                            -- end of code from book
1346
73: 
1347
74:                            procedure procedure_09_1_b is
1348

    
1349
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_09_ch_09_04.vhd
1350
ERROR: Parse error at line 66 column 56:
1351

    
1352
56: library stimulus;
1353
57: use stimulus.stimulus_generators.all;
1354
58: 
1355
59: architecture test of ch_09_04 is
1356
60: 
1357
61:   -- code from book
1358
62: 
1359
63:   -- MTI bug mt017
1360
64:   -- alias bv_increment is work.arithmetic_ops.increment [ bit_vector, integer ];
1361
65: 
1362
66:   alias int_increment is work.arithmetic_ops.increment [ integer, integer ];
1363
                                                           ^
1364
67: 
1365
68:   -- workaround to avoid MTI bug mt018
1366
69:   -- alias "*" is "and" [ bit, bit return bit ];
1367
70: 
1368
71:   alias "*" is std.standard."and" [ bit, bit return bit ];
1369
72: 
1370
73:   -- alias "+" is "or" [ bit, bit return bit ];
1371
74: 
1372
75:   alias "+" is std.standard."or" [ bit, bit return bit ];
1373
76: 
1374

    
1375
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_09_fg_09_01.vhd
1376
ERROR: Parse error at line 51 column 23:
1377

    
1378
41: 
1379
42: 
1380
43: entity controller_system is
1381
44: end entity controller_system;
1382
45: 
1383
46: -- end not in book
1384
47: 
1385
48: 
1386
49: 
1387
50: library ieee;  use ieee.std_logic_1164.all;
1388
51: use work.alu_types.all, work.io_types.all;
1389
                          ^
1390
52: 
1391
53: architecture structural of controller_system is
1392
54: 
1393
55:   alias alu_data_width is work.alu_types.data_width;
1394
56:   alias io_data_width is work.io_types.data_width;
1395
57: 
1396
58:   signal alu_in1, alu_in2,
1397
59:     alu_result : std_logic_vector(0 to alu_data_width - 1);
1398
60:   signal  io_data : std_logic_vector(0 to io_data_width - 1);
1399
61:   -- . . .
1400

    
1401
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_09_fg_09_03.vhd
1402
ERROR: Parse error at line 85 column 52:
1403

    
1404
75: 
1405
76: 
1406
77: -- code from book
1407
78: 
1408
79: package DMA_controller_types_and_utilities is
1409
80: 
1410
81:   alias word is work.cpu_types.word;
1411
82:   alias address is work.cpu_types.address;
1412
83:   alias status_value is work.cpu_types.status_value;
1413
84: 
1414
85:   alias "+" is work.bit_vector_unsigned_arithmetic."+"
1415
                                                       ^
1416
86:     [ bit_vector, bit_vector return bit_vector ];
1417
87: 
1418
88:   -- . . .
1419
89: 
1420
90: end package DMA_controller_types_and_utilities;
1421
91: 
1422
92: -- end code from book
1423
93: 
1424
94: 
1425

    
1426
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_10_bvat-b.vhd
1427
ERROR: Parse error at line 29 column 19:
1428

    
1429
19: 
1430
20: -- ---------------------------------------------------------------------
1431
21: --
1432
22: -- $Id: ch_10_bvat-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
1433
23: -- $Revision: 1.3 $
1434
24: --
1435
25: -- ---------------------------------------------------------------------
1436
26: 
1437
27: library bv_utilities;
1438
28: 
1439
29: use std.textio.all, bv_utilities.bv_arithmetic.all;
1440
                      ^
1441
30: 
1442
31: architecture bench of bv_test is
1443
32:   
1444
33: begin
1445
34: 
1446
35:   process is
1447
36: 
1448
37:             variable L : line;
1449
38:           variable byte : bit_vector(0 to 7);
1450
39:           variable word : bit_vector(1 to 32);
1451

    
1452
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_11_ch_11_01.vhd
1453
ERROR: Parse error at line 41 column 33:
1454

    
1455
31: 
1456
32: ----------------------------------------------------------------
1457
33: 
1458
34: 
1459
35: architecture test of ch_11_01 is
1460
36: 
1461
37:   type MVL4_ulogic is ('X', '0', '1', 'Z');  -- unresolved logic type
1462
38: 
1463
39:   -- code from book:
1464
40: 
1465
41:   type small_int is range 1 to 4;
1466
                                    ^
1467
42:   type small_array is array (small_int range <>) of -- . . . ;
1468
43:     -- not in book
1469
44:     MVL4_ulogic;
1470
45:   -- end not in book
1471
46: 
1472
47:   -- end of code from book
1473
48: 
1474
49:   type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic;
1475
50:   constant resolution_table : table :=
1476
51:     --  'X'  '0'  '1'  'Z'
1477

    
1478
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_12_ch_12_01.vhd
1479
ERROR: Parse error at line 71 column 39:
1480

    
1481
61:     generic map ( Tpd => 2 ns )
1482
62:     port map ( a => sig1,  b => sig2,  y => sig_out );
1483
63: 
1484
64:   gate2 : entity work.and2(simple)
1485
65:     generic map ( Tpd => 3 ns )
1486
66:     port map ( a => a1,  b => b1,  y => sig1 );
1487
67: 
1488
68:   -- end code from book
1489
69: 
1490
70:   stimulus : all_possible_values ( bv => test_vector,
1491
71:        delay_between_values => 10 ns );
1492
                                          ^
1493
72: 
1494
73:   (sig2, a1, b1) <= test_vector;
1495
74: 
1496
75: end architecture test;
1497
76: 
1498

    
1499
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_12_fg_12_02.vhd
1500
ERROR: Parse error at line 51 column 22:
1501

    
1502
41:   check_setup : process is
1503
42:   begin
1504
43:     wait until clk = '1';
1505
44:     assert d'last_event >= Tsu_d_clk
1506
45:       report "setup violation";
1507
46:   end process check_setup;
1508
47: 
1509
48:   check_hold : process is
1510
49:   begin
1511
50:     wait until clk'delayed(Th_d_clk) = '1';
1512
51:     assert d'delayed'last_event >= Th_d_clk
1513
                         ^
1514
52:       report "hold violation";
1515
53:   end process check_hold;
1516
54: 
1517
55: end architecture basic;
1518
56: 
1519
57: -- end code from book
1520
58: 
1521
59: 
1522
60: 
1523
61: entity fg_12_02 is
1524

    
1525
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_13_ch_13_01.vhd
1526
ERROR: Parse error at line 71 column 5:
1527

    
1528
61: 
1529
62: -- end code from book
1530
63: 
1531
64: 
1532
65: configuration ch_13_01_test of ch_13_01 is
1533
66: 
1534
67:   for test
1535
68: 
1536
69:     -- code from book
1537
70: 
1538
71:     for gate1 : nand3
1539
        ^
1540
72:       use entity work.nand2(basic);
1541
73:     end for;
1542
74: 
1543
75:     -- end code from book
1544
76: 
1545
77:   end for;
1546
78: 
1547
79: end configuration ch_13_01_test;
1548
80: 
1549

    
1550
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_13_fg_13_01.vhd
1551
ERROR: Parse error at line 111 column 5:
1552

    
1553
101: -- end code from book
1554
102: 
1555
103: 
1556
104: 
1557
105: configuration fg_13_01 of reg4 is
1558
106: 
1559
107:   for struct
1560
108: 
1561
109:     -- code from book (in text)
1562
110: 
1563
111:     for bit0, bit1 : flipflop
1564
         ^
1565
112:       use entity work.edge_triggered_Dff(basic);
1566
113:     end for;
1567
114: 
1568
115:     -- end code from book
1569
116: 
1570
117:   end for;
1571
118: 
1572
119: end configuration fg_13_01;
1573
120: 
1574

    
1575
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_13_fg_13_05.vhd
1576
ERROR: Parse error at line 37 column 5:
1577

    
1578
27: -- code from book
1579
28: 
1580
29: library star_lib;
1581
30: --use star_lib.edge_triggered_Dff;
1582
31: use star_lib.all;
1583
32: 
1584
33: configuration reg4_gate_level of reg4 is
1585
34: 
1586
35:   for struct  -- architecture of reg4
1587
36: 
1588
37:     for bit0 : flipflop
1589
        ^
1590
38:       use entity star_lib.edge_triggered_Dff(hi_fanout);
1591
39:     end for;
1592
40: 
1593
41:     for others : flipflop
1594
42:       use entity star_lib.edge_triggered_Dff(basic);
1595
43:     end for;
1596
44: 
1597
45:   end for;  -- end of architecture struct
1598
46: 
1599
47: end configuration reg4_gate_level;
1600

    
1601
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_13_fg_13_07.vhd
1602
ERROR: Parse error at line 31 column 5:
1603

    
1604
21: --
1605
22: -- $Id: ch_13_fg_13_07.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
1606
23: -- $Revision: 1.1.1.1 $
1607
24: --
1608
25: -- ---------------------------------------------------------------------
1609
26: 
1610
27: configuration counter_down_to_gate_level of counter is
1611
28: 
1612
29:   for registered
1613
30: 
1614
31:     for all : digit_register
1615
        ^
1616
32:       use configuration work.reg4_gate_level;
1617
33:     end for;
1618
34: 
1619
35:     -- . . .    -- bindings for other component instances
1620
36: 
1621
37:   end for;  -- end of architecture registered
1622
38: 
1623
39: end configuration counter_down_to_gate_level;
1624
40: 
1625
41: 
1626

    
1627
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_13_fg_13_08.vhd
1628
ERROR: Parse error at line 35 column 5:
1629

    
1630
25: -- ---------------------------------------------------------------------
1631
26: 
1632
27: library star_lib;
1633
28: --use star_lib.edge_triggered_dff;
1634
29: use star_lib.all;
1635
30: 
1636
31: configuration full of counter is
1637
32: 
1638
33:   for registered  -- architecture of counter
1639
34: 
1640
35:     for all : digit_register
1641
        ^
1642
36:       use entity work.reg4(struct);
1643
37: 
1644
38:       for struct  -- architecture of reg4
1645
39: 
1646
40:         for bit0 : flipflop
1647
41:           use entity edge_triggered_Dff(hi_fanout);
1648
42:         end for;
1649
43: 
1650
44:         for others : flipflop
1651
45:           use entity edge_triggered_Dff(basic);
1652

    
1653
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_13_fg_13_09.vhd
1654
ERROR: Parse error at line 46 column 31:
1655

    
1656
36: 
1657
37:   --use work.counter_types.digit;
1658
38:   use work.counter_types.all;
1659
39: 
1660
40:   signal reset_to_midnight, seconds_clk : bit;
1661
41:   signal seconds_units, seconds_tens : digit;
1662
42:   -- . . .
1663
43: 
1664
44: begin
1665
45: 
1666
46:   seconds : configuration work.counter_down_to_gate_level
1667
                                  ^
1668
47:     port map ( clk => seconds_clk, clr => reset_to_midnight,
1669
48:                q0 => seconds_units, q1 => seconds_tens );
1670
49: 
1671
50:   -- . . .
1672
51: 
1673
52:   -- not in book
1674
53: 
1675
54:   clk_gen : seconds_clk <= not seconds_clk after 20 ns;
1676
55: 
1677
56:   clr_gen : reset_to_midnight <= '1' after 95 ns,
1678

    
1679
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_13_fg_13_12.vhd
1680
ERROR: Parse error at line 31 column 5:
1681

    
1682
21: --
1683
22: -- $Id: ch_13_fg_13_12.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
1684
23: -- $Revision: 1.2 $
1685
24: --
1686
25: -- ---------------------------------------------------------------------
1687
26: 
1688
27: configuration controller_with_timing of controller is
1689
28: 
1690
29:   for structural
1691
30: 
1692
31:     for state_reg : reg
1693
        ^
1694
32:       use entity work.reg(gate_level)
1695
33:         generic map ( t_setup => 200 ps, t_hold => 150 ps, t_pd => 150 ps,
1696
34:                       width => width );
1697
35:     end for;
1698
36: 
1699
37:     -- . . .
1700
38: 
1701
39:   end for;
1702
40: 
1703
41: end configuration controller_with_timing;
1704

    
1705
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_13_fg_13_13.vhd
1706
ERROR: Parse error at line 67 column 35:
1707

    
1708
57:   interface_decoder : component decoder_2_to_4
1709
58:     generic map ( prop_delay => 4 ns )
1710
59:     port map ( in0 => addr(4), in1 => addr(5),
1711
60:                out0 => interface_a_select, out1 => interface_b_select,
1712
61:                out2 => interface_c_select, out3 => interface_d_select );
1713
62: 
1714
63:   -- . . .
1715
64: 
1716
65:   -- not in book
1717
66: 
1718
67:   all_possible_values(addr, 10 ns);
1719
                                      ^
1720
68: 
1721
69:   -- end not in book
1722
70: 
1723
71: end architecture structure;
1724
72: 
1725

    
1726
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_13_fg_13_14.vhd
1727
ERROR: Parse error at line 44 column 7:
1728

    
1729
34: 
1730
35: -- not in book
1731
36: 
1732
37: architecture basic of decoder_3_to_8 is
1733
38:     subtype bv_vec3 is bit_vector (2 downto 0);
1734
39: begin
1735
40: 
1736
41:   process (enable, s2, s1, s0) is
1737
42:   begin
1738
43:     if enable = '0' then
1739
44:       (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000000");
1740
          ^
1741
45:     else
1742
46:       case bv_vec3'(s2, s1, s0) is
1743
47:         when "000" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000001");
1744
48:         when "001" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000010");
1745
49:         when "010" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00000100");
1746
50:         when "011" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00001000");
1747
51:         when "100" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00010000");
1748
52:         when "101" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("00100000");
1749
53:         when "110" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("01000000");
1750
54:         when "111" => (y7, y6, y5, y4, y3, y2, y1, y0) <= bit_vector'("10000000");
1751

    
1752
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_13_fg_13_15.vhd
1753
ERROR: Parse error at line 31 column 5:
1754

    
1755
21: --
1756
22: -- $Id: ch_13_fg_13_15.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
1757
23: -- $Revision: 1.2 $
1758
24: --
1759
25: -- ---------------------------------------------------------------------
1760
26: 
1761
27: configuration computer_structure of computer_system is
1762
28: 
1763
29:   for structure
1764
30: 
1765
31:     for interface_decoder : decoder_2_to_4
1766
        ^
1767
32:       use entity work.decoder_3_to_8(basic)
1768
33:         generic map ( Tpd_01 => prop_delay, Tpd_10 => prop_delay )
1769
34:         port map ( s0 => in0, s1 => in1, s2 => '0',
1770
35:                    enable => '1',
1771
36:                    y0 => out0, y1 => out1, y2 => out2, y3 => out3,
1772
37:                    y4 => open, y5 => open, y6 => open, y7 => open );
1773
38:     end for;
1774
39: 
1775
40:     -- . . .
1776
41: 
1777

    
1778
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_13_fg_13_18.vhd
1779
ERROR: Parse error at line 54 column 5:
1780

    
1781
44: end architecture behavioral;
1782
45: 
1783
46: -- code from book
1784
47: 
1785
48: library chips;
1786
49: 
1787
50: configuration intermediate of single_board_computer is
1788
51: 
1789
52:   for structural
1790
53: 
1791
54:     for cpu : processor
1792
        ^
1793
55:       use entity chips.XYZ3000_cpu(full_function)
1794
56:         port map ( clock => clk, addr_data => a_d, -- . . . );
1795
57:                    -- not in book
1796
58:                    other_port => open );
1797
59:       -- end not in book
1798
60:     end for;
1799
61: 
1800
62:     for main_memory : memory
1801
63:       use entity work.memory_array(behavioral);
1802
64:     end for;
1803

    
1804
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_13_fg_13_19.vhd
1805
ERROR: Parse error at line 55 column 3:
1806

    
1807
45: -- code from book
1808
46: 
1809
47: library gate_lib;
1810
48: 
1811
49: architecture ideal of logic_block is
1812
50: 
1813
51:   component nand2 is
1814
52:                     port ( in1, in2 : in bit;  result : out bit );
1815
53:   end component nand2;
1816
54: 
1817
55:   for all : nand2
1818
      ^
1819
56:     use entity gate_lib.nand3(behavioral)
1820
57:     port map ( a => in1, b => in2, c => '1', y => result );
1821
58: 
1822
59:   -- . . .    -- other declarations
1823
60: 
1824
61:   -- not in book
1825
62:   signal s1, s2, s3 : bit := '0';
1826
63: 
1827
64: begin
1828
65: 
1829

    
1830
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_13_fg_13_20.vhd
1831
ERROR: Parse error at line 46 column 18:
1832

    
1833
36: 
1834
37:                architecture structural of control_section is
1835
38: 
1836
39:                  component reg is
1837
40:                                  generic ( width : positive );
1838
41:                                port ( clk : in std_logic;
1839
42:                                       d : in std_logic_vector(0 to width - 1);
1840
43:                                       q : out std_logic_vector(0 to width - 1) );
1841
44:                  end component reg;
1842
45: 
1843
46:                  for flag_reg : reg
1844
                     ^
1845
47:                    use entity work.reg(gate_level)
1846
48:                    -- workaround for MTI bug mt023
1847
49:                    --  reverted for ghdl
1848
50:                    port map ( clock => clk, data_in => d, data_out => q );
1849
51:                    -- port map ( clock => clk, data_in => d, data_out => q, reset_n => '1' );
1850
52:                  -- end workaround
1851
53: 
1852
54:                  -- . . .
1853
55: 
1854
56:                  -- not in book
1855

    
1856
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_13_fg_13_22.vhd
1857
ERROR: Parse error at line 31 column 5:
1858

    
1859
21: --
1860
22: -- $Id: ch_13_fg_13_22.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
1861
23: -- $Revision: 1.2 $
1862
24: --
1863
25: -- ---------------------------------------------------------------------
1864
26: 
1865
27: configuration controller_with_timing of control_section is
1866
28: 
1867
29:   for structural
1868
30: 
1869
31:     for flag_reg : reg
1870
        ^
1871
32:       generic map ( t_setup => 200 ps, t_hold => 150 ps,
1872
33:                     t_pd => 150 ps, width => width )
1873
34:         -- workaround for MTI bug mt023
1874
35:         -- port map ( reset_n => '1');
1875
36:         ;
1876
37:       -- end workaround
1877
38:     end for;
1878
39: 
1879
40:     -- . . .
1880
41: 
1881

    
1882
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_13_fg_13_23.vhd
1883
ERROR: Parse error at line 87 column 18:
1884

    
1885
77: -- code from book
1886
78: 
1887
79:                architecture detailed_timing of interlock_control is
1888
80: 
1889
81:                  component nor_gate is
1890
82:                                       generic ( input_width : positive );
1891
83:                                     port ( input : in std_logic_vector(0 to input_width - 1);
1892
84:                                            output : out std_logic );
1893
85:                  end component nor_gate;
1894
86: 
1895
87:                  for ex_interlock_gate : nor_gate
1896
                     ^
1897
88:                    use entity cell_lib.nor_gate(primitive)
1898
89:                    generic map ( width => input_width,
1899
90:                                  Tpd01 => 250 ps, Tpd10 => 200 ps );  -- estimates
1900
91: 
1901
92:                  -- . . .
1902
93: 
1903
94:                  -- not in book
1904
95:                  signal reg_access_hazard, load_hazard, stall_ex_n : std_logic;
1905
96:                  -- end not in book
1906
97: 
1907

    
1908
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_13_fg_13_24.vhd
1909
ERROR: Parse error at line 43 column 5:
1910

    
1911
33:   -- . . .
1912
34: 
1913
35: end configuration interlock_control_with_estimates;
1914
36: 
1915
37: --------------------------------------------------
1916
38: 
1917
39: configuration interlock_control_with_actual of interlock_control is
1918
40: 
1919
41:   for detailed_timing
1920
42: 
1921
43:     for ex_interlock_gate : nor_gate
1922
        ^
1923
44:       generic map ( Tpd01 => 320 ps, Tpd10 => 230 ps );
1924
45:     end for;
1925
46: 
1926
47:     -- . . .
1927
48: 
1928
49:   end for;
1929
50: 
1930
51: end configuration interlock_control_with_actual;
1931
52: 
1932

    
1933
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_13_fg_13_25.vhd
1934
ERROR: Parse error at line 54 column 3:
1935

    
1936
44: 
1937
45: -- code from book
1938
46: 
1939
47: architecture gate_level of misc_logic is
1940
48: 
1941
49:   component nand3 is
1942
50:                     generic ( Tpd : delay_length );
1943
51:                   port ( a, b, c : in bit;  y : out bit );
1944
52:   end component nand3;
1945
53: 
1946
54:   for all : nand3
1947
      ^
1948
55:     use entity project_lib.nand3(basic);
1949
56: 
1950
57:   -- . . .
1951
58: 
1952
59:   -- not in book
1953
60:   signal sig1, sig2, sig3, out_sig : bit;
1954
61:   signal test_vector : bit_vector(1 to 3);
1955
62:   -- end not in book
1956
63: 
1957
64: begin
1958

    
1959
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_13_fg_13_26.vhd
1960
ERROR: Parse error at line 31 column 5:
1961

    
1962
21: --
1963
22: -- $Id: ch_13_fg_13_26.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
1964
23: -- $Revision: 1.2 $
1965
24: --
1966
25: -- ---------------------------------------------------------------------
1967
26: 
1968
27: configuration misc_logic_reconfigured of misc_logic is
1969
28: 
1970
29:   for gate_level
1971
30: 
1972
31:     for gate1 : nand3
1973
        ^
1974
32:       generic map ( Tpd => 1.6 ns )
1975
33:         port map ( a => c, c => a, b => b, y => y );
1976
34:     end for;
1977
35: 
1978
36:   end for;
1979
37: 
1980
38: end configuration misc_logic_reconfigured;
1981
39: 
1982

    
1983
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_14_ch_14_01.vhd
1984
ERROR: Parse error at line 79 column 30:
1985

    
1986
69:                    output(0) <= input;
1987
70:                  end generate degenerate_tree;
1988
71: 
1989
72:                  compound_tree : if height > 0 generate
1990
73: 
1991
74:                    buf_0 : buf
1992
75:                      port map ( a => input, y => buffered_input_0 );
1993
76: 
1994
77:                    -- code from book
1995
78: 
1996
79:                    block_0 : block
1997
                                 ^
1998
80:                      for subtree_0 : fanout_tree
1999
81:                        use entity work.fanout_tree(recursive);
2000
82:                    begin
2001
83:                      subtree_0 : fanout_tree
2002
84:                        generic map ( height => height - 1 )
2003
85:                        port map (  input => buffered_input_0,
2004
86:                                    output => output(0 to 2**(height - 1) - 1) );
2005
87:                    end block block_0;
2006
88: 
2007
89:                    -- end code from book
2008

    
2009
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_14_fg_14_01.vhd
2010
ERROR: Parse error at line 118 column 20:
2011

    
2012
108: 
2013
109: 
2014
110: -- code from book (in Figure 14-11)
2015
111: 
2016
112:                library cell_lib;
2017
113: 
2018
114:                configuration identical_cells of register_tristate is
2019
115: 
2020
116:                  for cell_level
2021
117: 
2022
118:                    for cell_array
2023
                        ^
2024
119: 
2025
120:                    for cell_storage : D_flipflop
2026
121:                    use entity cell_lib.D_flipflop(synthesized);
2027
122:                end for;
2028
123: 
2029
124:                for cell_buffer : tristate_buffer
2030
125:                  use entity cell_lib.tristate_buffer(synthesized);
2031
126:                end for;
2032
127: 
2033
128:                end for;
2034

    
2035
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_14_fg_14_06.vhd
2036
ERROR: Parse error at line 162 column 5:
2037

    
2038
152: end architecture test;
2039
153: 
2040
154: 
2041
155: 
2042
156: configuration fg_14_06_test of fg_14_06 is
2043
157: 
2044
158:   for test
2045
159: 
2046
160:     -- code from book (in text)
2047
161: 
2048
162:     for system_under_test : computer_system
2049
         ^
2050
163:       use entity work.computer_system(block_level)
2051
164:         generic map ( instrumented => true )
2052
165:         -- . . .
2053
166:         -- not in book
2054
167:         ;
2055
168:       -- end not in book
2056
169:     end for;
2057
170: 
2058
171:     -- end code from book
2059
172: 
2060

    
2061
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_14_fg_14_09.vhd
2062
ERROR: Parse error at line 59 column 47:
2063

    
2064
49: 
2065
50: 
2066
51: architecture general_purpose of bus_monitor is
2067
52: begin
2068
53: 
2069
54:   access_monitor : process is
2070
55: 
2071
56:                              variable access_count, ifetch_count,
2072
57:                            write_count, read_count : natural := 0;
2073
58:                            use std.textio;
2074
59:                            variable L : textio.line;
2075
                                                  ^
2076
60: 
2077
61:   begin
2078
62:     wait until mem_req = '1';
2079
63:     if ifetch = '1' then
2080
64:       ifetch_count := ifetch_count + 1;
2081
65:       if verbose then
2082
66:         textio.write(L, string'("Ifetch"));
2083
67:         textio.writeline(textio.output, L);
2084
68:       end if;
2085
69:     elsif write = '1' then
2086

    
2087
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_14_fg_14_10.vhd
2088
ERROR: Parse error at line 33 column 5:
2089

    
2090
23: -- $Revision: 1.2 $
2091
24: --
2092
25: -- ---------------------------------------------------------------------
2093
26: 
2094
27: configuration architectural of computer_system is
2095
28: 
2096
29:   for block_level
2097
30: 
2098
31:     -- . . .    -- component configurations for cpu and memory, etc
2099
32: 
2100
33:     for instrumentation
2101
        ^
2102
34: 
2103
35:       for cpu_bus_monitor : bus_monitor_pkg.bus_monitor
2104
36:                                              use entity work.bus_monitor(general_purpose)
2105
37:                                              generic map ( verbose => true, dump_stats => true );
2106
38:       end for;
2107
39: 
2108
40:     end for;
2109
41: 
2110
42:   end for;
2111
43: 
2112

    
2113
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_14_fg_14_12.vhd
2114
ERROR: Parse error at line 50 column 20:
2115

    
2116
40: 
2117
41: 
2118
42: -- code from book
2119
43: 
2120
44:                library chip_lib;  use chip_lib.all;
2121
45: 
2122
46:                configuration down_to_chips of memory_board is
2123
47: 
2124
48:                  for chip_level
2125
49: 
2126
50:                    for bank_array
2127
                       ^
2128
51: 
2129
52:                    for nibble_array
2130
53: 
2131
54:                    for a_DRAM : DRAM
2132
55:                    use entity DRAM_4M_by_4(chip_function);
2133
56:                end for;
2134
57: 
2135
58:                end for;
2136
59: 
2137
60:                end for;
2138

    
2139
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_14_fg_14_13.vhd
2140
ERROR: Parse error at line 63 column 20:
2141

    
2142
53: -- code from book
2143
54: 
2144
55:                library cell_lib;
2145
56: 
2146
57:                configuration last_high_drive of shift_reg is
2147
58: 
2148
59:                  for cell_level
2149
60: 
2150
61:                    -- workaround for MTI bug mt026
2151
62:                    -- for reg_array ( 0 to parallel_data'length - 2 )
2152
63:                    for reg_array ( 0 to 2 )
2153
                       ^
2154
64:                    -- end workaround
2155
65: 
2156
66:                    for first_cell
2157
67:                    for cell : master_slave_flipflop
2158
68:                    use entity cell_lib.ms_flipflop(normal_drive);
2159
69:                end for;
2160
70:                end for;
2161
71: 
2162
72:                for other_cell
2163
73:                  for cell : master_slave_flipflop
2164

    
2165
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_15_alu.vhd
2166
ERROR: Parse error at line 30 column 23:
2167

    
2168
20: -- ---------------------------------------------------------------------
2169
21: --
2170
22: -- $Id: ch_15_alu.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
2171
23: -- $Revision: 1.3 $
2172
24: --
2173
25: -- ---------------------------------------------------------------------
2174
26: 
2175
27: library ieee;
2176
28: use ieee.std_logic_1164.all;
2177
29: 
2178
30: use work.dlx_types.all,
2179
                          ^
2180
31:   work.alu_types.all;
2181
32: 
2182
33: entity alu is
2183
34:   generic ( Tpd : delay_length );
2184
35:   port ( s1 : in dlx_word;
2185
36:          s2 : in dlx_word;
2186
37:          result : out dlx_word;
2187
38:          func : in alu_func;
2188
39:          zero, negative, overflow : out std_logic );
2189
40: end entity alu;
2190

    
2191
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_15_crtl.vhd
2192
ERROR: Parse error at line 30 column 23:
2193

    
2194
20: -- ---------------------------------------------------------------------
2195
21: --
2196
22: -- $Id: ch_15_crtl.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
2197
23: -- $Revision: 1.3 $
2198
24: --
2199
25: -- ---------------------------------------------------------------------
2200
26: 
2201
27: library ieee;
2202
28: use ieee.std_logic_1164.all;
2203
29: 
2204
30: use work.dlx_types.all,
2205
                          ^
2206
31:   work.alu_types.all,
2207
32:   work.reg_file_types.all;
2208
33: 
2209
34: entity controller is
2210
35:   generic ( Tpd_clk_ctrl, Tpd_clk_const : delay_length;
2211
36:             debug : dlx_debug_control := none );
2212
37:   port ( phi1, phi2 : in std_logic;
2213
38:          reset : in std_logic;
2214
39:          halt : out std_logic;
2215
40:          width : out dlx_mem_width;
2216

    
2217
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_15_ctrl-b.vhd
2218
ERROR: Parse error at line 73 column 35:
2219

    
2220
63:                         ifetch <= '1' after Tpd_clk_ctrl;
2221
64:                         write_enable <= '0' after Tpd_clk_ctrl;
2222
65:                         mem_enable <= '1' after Tpd_clk_ctrl;
2223
66:                         -- wait until phi2, then enable IR input
2224
67:                         wait until rising_edge(phi2);
2225
68:                         ir_latch_en <= '1' after Tpd_clk_ctrl;
2226
69:                         -- wait until memory is ready at end of phi2
2227
70:                         loop 
2228
71:                           wait until falling_edge(phi2);
2229
72:                           if To_bit(reset) = '1' then
2230
73:                             return;
2231
                                      ^
2232
74:                           end if;
2233
75:                           exit when To_bit(ready) = '1';
2234
76:                         end loop;
2235
77:                         -- disable IR input and memory control signals
2236
78:                         ir_latch_en <= '0' after Tpd_clk_ctrl;
2237
79:                         mem_enable <= '0' after Tpd_clk_ctrl;
2238
80:                       end procedure bus_instruction_fetch;
2239
81: 
2240
82:                       procedure bus_data_read ( read_width : in dlx_mem_width ) is
2241
83:                       begin
2242

    
2243
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_15_dlx-b.vhd
2244
ERROR: Parse error at line 85 column 15:
2245

    
2246
75: 
2247
76: 
2248
77:     procedure bus_read ( address : in dlx_bv_address;
2249
78:                          data_width : in dlx_mem_width;
2250
79:                          instr_fetch : in std_logic;
2251
80:                          data : out dlx_bv_word ) is
2252
81: 
2253
82:     begin
2254
83:       wait until rising_edge(phi1);
2255
84:       if To_bit(reset) = '1' then
2256
85:         return;
2257
                  ^
2258
86:       end if;
2259
87:       a <= To_X01(address) after Tpd_clk_out;
2260
88:       width <= data_width after Tpd_clk_out;
2261
89:       ifetch <= instr_fetch after Tpd_clk_out;
2262
90:       mem_enable <= '1' after Tpd_clk_out;
2263
91:       loop 
2264
92:         wait until falling_edge(phi2);
2265
93:         if To_bit(reset) = '1' then
2266
94:           return;
2267
95:         end if;
2268

    
2269
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_15_dlx-r.vhd
2270
ERROR: Parse error at line 27 column 23:
2271

    
2272
17: -- along with VESTs; if not, write to the Free Software Foundation,
2273
18: -- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
2274
19: 
2275
20: -- ---------------------------------------------------------------------
2276
21: --
2277
22: -- $Id: ch_15_dlx-r.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
2278
23: -- $Revision: 1.3 $
2279
24: --
2280
25: -- ---------------------------------------------------------------------
2281
26: 
2282
27: use work.alu_types.all,
2283
                          ^
2284
28:   work.reg_file_types.all;
2285
29: 
2286
30: architecture rtl of dlx is
2287
31: 
2288
32:   component alu is
2289
33:                   port ( s1 : in dlx_word;
2290
34:                          s2 : in dlx_word;
2291
35:                          result : out dlx_word;
2292
36:                          func : in alu_func;
2293
37:                          zero, negative, overflow : out std_logic );
2294

    
2295
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_15_dlxi-b.vhd
2296
ERROR: Parse error at line 135 column 65:
2297

    
2298
125:           index := index + 3;
2299
126:         when 1 =>
2300
127:           result(index to index + 2) := "FSR";
2301
128:           index := index + 3;
2302
129:         when others =>
2303
130:           disassemble_reg(reg, 'S');
2304
131:       end case;
2305
132:     end procedure disassemble_special_reg;
2306
133: 
2307
134:     procedure disassemble_integer ( int : integer ) is
2308
135:       constant int_image_length : natural := integer'image(int)'length;
2309
                                                                     ^
2310
136:     begin
2311
137:       result(index to index + int_image_length - 1) := integer'image(int);
2312
138:       index := index + int_image_length;
2313
139:     end procedure disassemble_integer;
2314
140: 
2315
141:   begin
2316
142:     instr_opcode_num := bv_to_natural(instr_opcode);
2317
143:     instr_sp_func_num := bv_to_natural(instr_sp_func);
2318
144:     instr_fp_func_num := bv_to_natural(instr_fp_func);
2319
145:     rs1 := bv_to_natural(instr_rs1);
2320

    
2321
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_15_dlxr.vhd
2322
ERROR: Parse error at line 31 column 5:
2323

    
2324
21: --
2325
22: -- $Id: ch_15_dlxr.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
2326
23: -- $Revision: 1.1.1.1 $
2327
24: --
2328
25: -- ---------------------------------------------------------------------
2329
26: 
2330
27: configuration dlx_rtl of dlx is
2331
28: 
2332
29:   for rtl
2333
30: 
2334
31:     for alu_s1_reg : latch
2335
        ^
2336
32:       use entity work.latch(behavior)
2337
33:         generic map ( Tpd => 2 ns );
2338
34:     end for;
2339
35: 
2340
36:     for alu_s2_reg : latch
2341
37:       use entity work.latch(behavior)
2342
38:         generic map ( Tpd => 2 ns );
2343
39:     end for;
2344
40: 
2345
41:     for the_alu : alu
2346

    
2347
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_15_dlxstsv.vhd
2348
ERROR: Parse error at line 31 column 5:
2349

    
2350
21: --
2351
22: -- $Id: ch_15_dlxstsv.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
2352
23: -- $Revision: 1.1.1.1 $
2353
24: --
2354
25: -- ---------------------------------------------------------------------
2355
26: 
2356
27: configuration dlx_test_verifier of dlx_test is
2357
28: 
2358
29:   for verifier
2359
30: 
2360
31:     for cg : clock_gen
2361
        ^
2362
32:       use entity work.clock_gen(behavior)
2363
33:         generic map ( Tpw => 8 ns, Tps => 2 ns );
2364
34:     end for;
2365
35: 
2366
36:     for mem : memory
2367
37:       use entity work.memory(preloaded)
2368
38:         generic map ( mem_size => 65536,
2369
39:                       Tac_first => 95 ns, Tac_burst => 35 ns, Tpd_clk_out => 2 ns );
2370
40:     end for;
2371
41: 
2372

    
2373
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_15_dlxtst-v.vhd
2374
ERROR: Parse error at line 105 column 26:
2375

    
2376
 95:                ifetch => ifetch_behav,
2377
 96:                mem_enable => mem_enable_behav, ready => ready_mem );
2378
 97: 
2379
 98:   proc_rtl : component dlx
2380
 99:     port map ( phi1 => phi1, phi2 => phi2, reset => reset, halt => halt_rtl,
2381
100:                a => a_rtl, d => d_rtl,
2382
101:                width => width_rtl, write_enable => write_enable_rtl,
2383
102:                ifetch => ifetch_rtl,
2384
103:                mem_enable => mem_enable_rtl, ready => ready_mem );
2385
104: 
2386
105:   verification_section : block is
2387
                              ^
2388
106:   begin
2389
107: 
2390
108:     fwd_data_from_mem_to_rtl : 
2391
109:       d_rtl <= d_behav when mem_enable_rtl = '1'
2392
110:                and write_enable_rtl = '0' else
2393
111:                disabled_dlx_word;
2394
112: 
2395
113:     monitor : process
2396
114: 
2397
115:       variable write_command_behav : boolean;
2398

    
2399
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_15_dlxtstb.vhd
2400
ERROR: Parse error at line 31 column 5:
2401

    
2402
21: --
2403
22: -- $Id: ch_15_dlxtstb.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
2404
23: -- $Revision: 1.1.1.1 $
2405
24: --
2406
25: -- ---------------------------------------------------------------------
2407
26: 
2408
27: configuration dlx_test_behavior of dlx_test is
2409
28: 
2410
29:   for bench
2411
30: 
2412
31:     for cg : clock_gen
2413
        ^
2414
32:       use entity work.clock_gen(behavior)
2415
33:         generic map ( Tpw => 8 ns, Tps => 2 ns );
2416
34:     end for;
2417
35: 
2418
36:     for mem : memory
2419
37:       use entity work.memory(preloaded)
2420
38:         generic map ( mem_size => 65536,
2421
39:                       Tac_first => 95 ns, Tac_burst => 35 ns, Tpd_clk_out => 2 ns );
2422
40:     end for;
2423
41: 
2424

    
2425
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_15_dlxtstr.vhd
2426
ERROR: Parse error at line 31 column 5:
2427

    
2428
21: --
2429
22: -- $Id: ch_15_dlxtstr.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
2430
23: -- $Revision: 1.1.1.1 $
2431
24: --
2432
25: -- ---------------------------------------------------------------------
2433
26: 
2434
27: configuration dlx_test_rtl of dlx_test is
2435
28: 
2436
29:   for bench
2437
30: 
2438
31:     for cg : clock_gen
2439
        ^
2440
32:       use entity work.clock_gen(behavior)
2441
33:         generic map ( Tpw => 8 ns, Tps => 2 ns );
2442
34:     end for;
2443
35: 
2444
36:     for mem : memory
2445
37:       use entity work.memory(preloaded)
2446
38:         generic map ( mem_size => 65536,
2447
39:                       Tac_first => 95 ns, Tac_burst => 35 ns, Tpd_clk_out => 2 ns );
2448
40:     end for;
2449
41: 
2450

    
2451
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_15_mem-fl.vhd
2452
ERROR: Parse error at line 29 column 35:
2453

    
2454
19: 
2455
20: -- ---------------------------------------------------------------------
2456
21: --
2457
22: -- $Id: ch_15_mem-fl.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
2458
23: -- $Revision: 1.3 $
2459
24: --
2460
25: -- ---------------------------------------------------------------------
2461
26: 
2462
27: library bv_utilities;
2463
28: 
2464
29: use bv_utilities.bv_arithmetic.all,
2465
                                      ^
2466
30:   std.textio.all;
2467
31: 
2468
32: architecture file_loaded of memory is
2469
33: begin
2470
34: 
2471
35:   mem_behavior : process is
2472
36: 
2473
37:                            constant high_address : natural := mem_size - 1;
2474
38: 
2475
39:                          type memory_array is
2476

    
2477
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_15_rf-b.vhd
2478
ERROR: Parse error at line 35 column 75:
2479

    
2480
25: -- ---------------------------------------------------------------------
2481
26: 
2482
27: library bv_utilities;
2483
28: 
2484
29: architecture behavior of reg_file is
2485
30: 
2486
31: begin
2487
32: 
2488
33:   reg: process ( a1, a2, a3, d3, write_en ) is
2489
34: 
2490
35:                                               use work.dlx_instr.reg_index,
2491
                                                                              ^
2492
36:                                               bv_utilities.bv_arithmetic.bv_to_natural;
2493
37: 
2494
38:                                             constant all_zeros : dlx_word := X"0000_0000";
2495
39: 
2496
40:                                             type register_array is array (reg_index range 1 to 31) of dlx_word;
2497
41: 
2498
42:                                             variable register_file : register_array;
2499
43:                                             variable reg_index1, reg_index2, reg_index3 : reg_index;
2500
44: 
2501
45:   begin
2502

    
2503
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_15_rf.vhd
2504
ERROR: Parse error at line 29 column 38:
2505

    
2506
19: 
2507
20: -- ---------------------------------------------------------------------
2508
21: --
2509
22: -- $Id: ch_15_rf.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
2510
23: -- $Revision: 1.2 $
2511
24: --
2512
25: -- ---------------------------------------------------------------------
2513
26: 
2514
27: library ieee;  use ieee.std_logic_1164.all;
2515
28: 
2516
29:                use work.dlx_types.all,
2517
                                         ^
2518
30:                  work.reg_file_types.all;
2519
31: 
2520
32:                entity reg_file is
2521
33:                  generic ( Tac : delay_length );
2522
34:                  port ( a1 : in reg_file_addr;
2523
35:                         q1 : out dlx_word;
2524
36:                         a2 : in reg_file_addr;
2525
37:                         q2 : out dlx_word;
2526
38:                         a3 : in reg_file_addr;
2527
39:                         d3 : in dlx_word;
2528

    
2529
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_16_ch_16_04.vhd
2530
ERROR: Parse error at line 54 column 3:
2531

    
2532
44:     else
2533
45:       return X"00000000";
2534
46:     end if;
2535
47:   end function resolve_words;
2536
48: 
2537
49:   subtype resolved_word is resolve_words word;
2538
50: 
2539
51:   -- code from book:
2540
52: 
2541
53:   signal memory_data_bus : resolved_word bus;
2542
54:   disconnect memory_data_bus : resolved_word after 3 ns;
2543
      ^
2544
55: 
2545
56:   -- end of code from book
2546
57: 
2547
58:   signal mem_sel, mem_write : boolean;
2548
59:   signal cache_data_bus : word;
2549
60: 
2550
61: begin
2551
62: 
2552
63: 
2553
64:   -- code from book:
2554

    
2555
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_16_ch_16_05.vhd
2556
ERROR: Parse error at line 56 column 3:
2557

    
2558
46:     end if;
2559
47:   end function resolve_words;
2560
48: 
2561
49:   subtype resolved_word is resolve_words word;
2562
50: 
2563
51:   -- code from book:
2564
52: 
2565
53:   signal source_bus_1, source_bus_2 : resolved_word bus;
2566
54:   signal address_bus : resolved_word bus;
2567
55: 
2568
56:   disconnect all : resolved_word after 2 ns;
2569
      ^
2570
57: 
2571
58:   -- end of code from book
2572
59: 
2573
60:   signal s : word;
2574
61:   signal g : boolean;
2575
62: 
2576
63: begin
2577
64: 
2578
65: 
2579
66:   b : block (g) is
2580

    
2581
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_16_ch_16_06.vhd
2582
ERROR: Parse error at line 56 column 3:
2583

    
2584
46:     end if;
2585
47:   end function resolve_words;
2586
48: 
2587
49:   subtype resolved_word is resolve_words word;
2588
50: 
2589
51:   signal source_bus_1, source_bus_2 : resolved_word bus;
2590
52:   signal address_bus : resolved_word bus;
2591
53: 
2592
54:   -- code from book:
2593
55: 
2594
56:   disconnect address_bus : resolved_word after 3 ns;
2595
      ^
2596
57: 
2597
58:   disconnect others : resolved_word after 2 ns;
2598
59: 
2599
60:   -- end of code from book
2600
61: 
2601
62:   signal s : word;
2602
63:   signal g : boolean;
2603
64: 
2604
65: begin
2605
66: 
2606

    
2607
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_16_fg_16_02.vhd
2608
ERROR: Parse error at line 86 column 32:
2609

    
2610
76:       -- not in book
2611
77:       stored_value := not stored_value;
2612
78:       -- end not in book
2613
79:     else
2614
80:       source1 <= null;
2615
81:     end if;
2616
82:   end process source1_reg;
2617
83: 
2618
84:   alu : perform_alu_op ( alu_opcode, source1, source2, destination, -- . . . );
2619
85:                          -- not in book
2620
86:                          open );
2621
                                   ^
2622
87:   -- end not in book
2623
88: 
2624
89:   -- . . .
2625
90: 
2626
91:   -- not in book
2627
92: 
2628
93:   process is
2629
94:   begin
2630
95:     wait for 10 ns;
2631
96:     source1_reg_out_en <= '1';
2632

    
2633
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_16_fg_16_05.vhd
2634
ERROR: Parse error at line 33 column 32:
2635

    
2636
23: -- $Revision: 1.2 $
2637
24: --
2638
25: -- ---------------------------------------------------------------------
2639
26: 
2640
27: use work.fg_16_04.all;
2641
28: 
2642
29: -- code from book (in text)
2643
30: 
2644
31: entity tri_state_reg is
2645
32:   port ( d : in resolved_byte;
2646
33:          q : out resolved_byte bus;
2647
                                   ^
2648
34:          clock, out_enable : in bit );
2649
35: end entity tri_state_reg;
2650
36: 
2651
37: -- end code from book
2652
38: 
2653
39: 
2654
40: 
2655
41: -- code from book
2656
42: 
2657
43: architecture behavioral of tri_state_reg is
2658

    
2659
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_16_fg_16_07.vhd
2660
ERROR: Parse error at line 44 column 38:
2661

    
2662
34: 
2663
35:                  constant reg0 : std_logic_vector(7 downto 0) := "00000000";
2664
36:                  constant reg1 : std_logic_vector(7 downto 0) := "11111111";
2665
37:                  signal dbus : std_logic_vector(7 downto 0);
2666
38:                  signal reg_sel, read, reg_addr : X01 := '0';
2667
39: 
2668
40:                begin
2669
41: 
2670
42:                  -- code from book
2671
43: 
2672
44:                  reg_read_selector : block (reg_sel = '1' and read = '1') is
2673
                                         ^
2674
45:                  begin
2675
46:                    dbus <= reg0 when guard and reg_addr = '0' else
2676
47:                            reg1 when guard and reg_addr = '1' else
2677
48:                            "ZZZZZZZZ";
2678
49:                  end block reg_read_selector;
2679
50: 
2680
51:                  -- end code from book
2681
52: 
2682
53:                  stimulus : process is
2683
54:                  begin
2684

    
2685
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_16_fg_16_08.vhd
2686
ERROR: Parse error at line 65 column 29:
2687

    
2688
55:   signal cache_miss, dirty, replace_section,
2689
56:     snoop_hit, flag_update : bit := '0';
2690
57:   constant tag_section0 : bit_vector(11 downto 0) := X"000";
2691
58:   constant tag_section1 : bit_vector(11 downto 0) := X"001";
2692
59:   constant set_index : bit_vector(15 downto 0) := X"6666";
2693
60:   constant snoop_address : word := X"88888888";
2694
61:   -- end not in book
2695
62: 
2696
63: begin
2697
64: 
2698
65:   cache_to_address_buffer : block ( cache_miss = '1' and dirty = '1' ) is
2699
                                ^
2700
66:   begin
2701
67:     address_bus <= guarded
2702
68:                    tag_section0 & set_index & B"0000" when replace_section = '0' else
2703
69:                    tag_section1 & set_index & B"0000";
2704
70:   end block cache_to_address_buffer;
2705
71: 
2706
72:   snoop_to_address_buffer : block ( snoop_hit = '1' and flag_update = '1' ) is
2707
73:   begin
2708
74:     address_bus <= guarded snoop_address(31 downto 4) & B"0000";
2709
75:   end block snoop_to_address_buffer;
2710

    
2711
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_16_fg_16_09.vhd
2712
ERROR: Parse error at line 39 column 22:
2713

    
2714
29:   port ( enable : in bit;
2715
30:          d : in bit_vector(0 to width - 1);
2716
31:          q : out bit_vector(0 to width - 1) );
2717
32: end entity latch;
2718
33: 
2719
34: --------------------------------------------------
2720
35: 
2721
36: architecture behavioral of latch is
2722
37: begin
2723
38: 
2724
39:   transfer_control : block ( enable = '1' ) is
2725
                         ^
2726
40:   begin
2727
41:     q <= guarded d;
2728
42:   end block transfer_control;
2729
43: 
2730
44: end architecture behavioral;
2731
45: 
2732
46: 
2733
47: -- not in book
2734
48: 
2735
49: entity fg_16_09 is
2736

    
2737
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_16_fg_16_10.vhd
2738
ERROR: Parse error at line 63 column 9:
2739

    
2740
53:   signal address_bus : resolve_word word bus;
2741
54:   signal hold_req : bit;
2742
55:   -- . . .
2743
56: 
2744
57:   -- not in book
2745
58:   signal clk : bit := '0';
2746
59:   -- end not in book
2747
60: 
2748
61: begin
2749
62: 
2750
63:   cpu : block is
2751
            ^
2752
64: 
2753
65:                 signal guard : boolean := false;
2754
66:               signal cpu_internal_address : word;
2755
67:               -- . . .
2756
68: 
2757
69:   begin
2758
70: 
2759
71:     cpu_address_driver:
2760
72:       address_bus <= guarded cpu_internal_address;
2761
73: 
2762

    
2763
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_16_fg_16_13.vhd
2764
ERROR: Parse error at line 35 column 22:
2765

    
2766
25: -- ---------------------------------------------------------------------
2767
26: 
2768
27: architecture detailed_timing of counter is
2769
28: 
2770
29:   signal reset_ipd,                   -- data input port delayed
2771
30:     clk_ipd : bit;               -- clock input port delayed
2772
31:   signal q_zd : bit_vector(q'range);  -- q output with zero delay
2773
32: 
2774
33: begin
2775
34: 
2776
35:   input_port_delay : block is
2777
                         ^
2778
36:   begin
2779
37:     reset_ipd <= reset after tipd_reset;
2780
38:     clk_ipd <= clk after tipd_clk;
2781
39:   end block input_port_delay;
2782
40: 
2783
41:   functionality : block is
2784
42: 
2785
43:                           function increment ( bv : bit_vector ) return bit_vector is
2786
44:     variable result : bit_vector(bv'range) := bv;
2787
45:     variable carry : bit := '1';
2788

    
2789
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_16_fg_16_14.vhd
2790
ERROR: Parse error at line 44 column 9:
2791

    
2792
34: 
2793
35: architecture contrived of example_entity is
2794
36: 
2795
37:   constant sig_width : positive := 16;
2796
38:   signal s1, s2, s3 : bit_vector (0 to sig_width - 1);
2797
39:   signal sel : bit;
2798
40:   -- . . .
2799
41: 
2800
42: begin
2801
43: 
2802
44:   mux : block is
2803
            ^
2804
45:                 generic ( width : positive );
2805
46:               generic map ( width => sig_width );
2806
47:               port ( d0, d1 : in bit_vector(0 to width - 1);
2807
48:                      y : out bit_vector(0 to width - 1);
2808
49:                      sel : in bit);
2809
50:               port map ( d0 => s1, d1=> s2, y => s3, sel => sel );
2810
51: 
2811
52:               constant zero : bit_vector(0 to width - 1) := ( others => '0' );
2812
53:               signal gated_d0, gated_d1 : bit_vector(0 to width - 1);
2813
54: 
2814

    
2815
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_16_fg_16_15.vhd
2816
ERROR: Parse error at line 45 column 18:
2817

    
2818
35: 
2819
36:   component subcircuit is
2820
37:                          port ( a, b : in bit;  y1, y2 : out bit );
2821
38:   end component subcircuit;
2822
39: 
2823
40:   signal delayed_in1, delayed_in2, delayed_in3 : bit;
2824
41:   signal undelayed_out1, undelayed_out2 : bit;
2825
42: 
2826
43: begin
2827
44: 
2828
45:   input_delays : block is
2829
                     ^
2830
46:   begin
2831
47:     delayed_in1 <= in1 after inpad_delay;
2832
48:     delayed_in2 <= in2 after inpad_delay;
2833
49:     delayed_in3 <= in3 after inpad_delay;
2834
50:   end block input_delays;
2835
51: 
2836
52:   functionality : block is
2837
53:                           signal intermediate : bit;
2838
54:   begin
2839
55:     cell1 : component subcircuit
2840

    
2841
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_17_ch_17_01.vhd
2842
ERROR: Parse error at line 43 column 33:
2843

    
2844
33: 
2845
34: 
2846
35: architecture test of ch_17_01 is
2847
36: begin
2848
37: 
2849
38: 
2850
39:   process is
2851
40: 
2852
41:             -- code from book:
2853
42: 
2854
43:             type natural_ptr is access natural;
2855
                                    ^
2856
44: 
2857
45:           variable count : natural_ptr;
2858
46: 
2859
47:           -- end of code from book
2860
48: 
2861
49:   begin
2862
50: 
2863
51:     -- code from book:
2864
52: 
2865
53:     count := new natural;
2866

    
2867
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_17_ch_17_02.vhd
2868
ERROR: Parse error at line 48 column 32:
2869

    
2870
38: 
2871
39:   process is
2872
40: 
2873
41:             -- code from book:
2874
42: 
2875
43:             type stimulus_record is record
2876
44:                                       stimulus_time : time;
2877
45:                                       stimulus_value : bit_vector(0 to 3);
2878
46:                                     end record stimulus_record;
2879
47: 
2880
48:           type stimulus_ptr is access stimulus_record;
2881
                                   ^
2882
49: 
2883
50:           variable bus_stimulus : stimulus_ptr;
2884
51: 
2885
52:           -- end of code from book
2886
53: 
2887
54:   begin
2888
55: 
2889
56:     -- code from book:
2890
57: 
2891
58:     bus_stimulus := new stimulus_record'( 20 ns, B"0011" );
2892

    
2893
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_17_ch_17_03.vhd
2894
ERROR: Parse error at line 41 column 33:
2895

    
2896
31: 
2897
32: ----------------------------------------------------------------
2898
33: 
2899
34: 
2900
35: architecture test of ch_17_03 is
2901
36: begin
2902
37: 
2903
38: 
2904
39:   process is
2905
40: 
2906
41:             type natural_ptr is access natural;
2907
                                    ^
2908
42: 
2909
43:           -- code from book:
2910
44: 
2911
45:           variable count1, count2 : natural_ptr;
2912
46: 
2913
47:           -- end of code from book
2914
48: 
2915
49:   begin
2916
50: 
2917
51:     -- code from book:
2918

    
2919
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_17_ch_17_04.vhd
2920
ERROR: Parse error at line 48 column 32:
2921

    
2922
38: 
2923
39:   process is
2924
40: 
2925
41:             -- code from book:
2926
42: 
2927
43:             type stimulus_record is record
2928
44:                                       stimulus_time : time;
2929
45:                                       stimulus_value : bit_vector(0 to 3);
2930
46:                                     end record stimulus_record;
2931
47: 
2932
48:           type stimulus_ptr is access stimulus_record;
2933
                                   ^
2934
49: 
2935
50:           variable bus_stimulus : stimulus_ptr;
2936
51: 
2937
52:           -- end of code from book
2938
53: 
2939
54:   begin
2940
55: 
2941
56:     bus_stimulus := new stimulus_record;
2942
57: 
2943
58:     bus_stimulus.all := stimulus_record'(20 ns, B"0011");
2944

    
2945
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_17_ch_17_05.vhd
2946
ERROR: Parse error at line 44 column 34:
2947

    
2948
34: 
2949
35: architecture test of ch_17_05 is
2950
36: begin
2951
37: 
2952
38: 
2953
39:   process is
2954
40: 
2955
41:             -- code from book:
2956
42: 
2957
43:             type coordinate is array (1 to 3) of real;
2958
44:           type coordinate_ptr is access coordinate;
2959
                                     ^
2960
45: 
2961
46:           variable origin : coordinate_ptr := new coordinate'(0.0, 0.0, 0.0);
2962
47: 
2963
48:           type time_array is array (positive range <>) of time;
2964
49:           variable activation_times : time_array(1 to 100);
2965
50: 
2966
51:           -- end of code from book
2967
52: 
2968
53:   begin
2969
54: 
2970

    
2971
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_17_ch_17_06.vhd
2972
ERROR: Parse error at line 48 column 29:
2973

    
2974
38: 
2975
39:   process is
2976
40: 
2977
41:             -- code from book:
2978
42: 
2979
43:             type value_cell is record
2980
44:                                  value : bit_vector(0 to 3);
2981
45:                                  next_cell : value_ptr;
2982
46:                                end record value_cell;
2983
47: 
2984
48:           type value_ptr is access value_cell;
2985
                                ^
2986
49: 
2987
50:           -- end of code from book
2988
51: 
2989
52:   begin
2990
53: 
2991
54:     wait;
2992
55:   end process;
2993
56: 
2994
57: 
2995
58: end architecture test;
2996

    
2997
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_17_ch_17_07.vhd
2998
ERROR: Parse error at line 43 column 28:
2999

    
3000
33: 
3001
34: 
3002
35: architecture test of ch_17_07 is
3003
36: begin
3004
37: 
3005
38: 
3006
39:   process is
3007
40: 
3008
41:             -- code from book:
3009
42: 
3010
43:             type value_cell;
3011
                               ^
3012
44: 
3013
45:           type value_ptr is access value_cell;
3014
46: 
3015
47:           type value_cell is record
3016
48:                                value : bit_vector(0 to 3);
3017
49:                                next_cell : value_ptr;
3018
50:                              end record value_cell;
3019
51: 
3020
52:           variable value_list : value_ptr;
3021
53: 
3022

    
3023
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_17_ch_17_08.vhd
3024
ERROR: Parse error at line 41 column 17:
3025

    
3026
31: 
3027
32: ----------------------------------------------------------------
3028
33: 
3029
34: 
3030
35: architecture test of ch_17_08 is
3031
36: 
3032
37:   type T is (t1, t2, t3);
3033
38: 
3034
39:   -- code from book:
3035
40: 
3036
41:   type T_ptr is access T;
3037
                    ^
3038
42: 
3039
43:   procedure deallocate ( P : inout T_ptr );
3040
44: 
3041
45:   -- end of code from book
3042
46: 
3043
47:   procedure deallocate ( P : inout T_ptr ) is
3044
48:   begin
3045
49:     null;
3046
50:   end procedure deallocate;
3047
51: 
3048

    
3049
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_17_ch_17_09.vhd
3050
ERROR: Parse error at line 41 column 28:
3051

    
3052
31: 
3053
32: ----------------------------------------------------------------
3054
33: 
3055
34: 
3056
35: architecture test of ch_17_09 is
3057
36: 
3058
37: begin
3059
38: 
3060
39:   process is
3061
40: 
3062
41:             type value_cell;
3063
                               ^
3064
42: 
3065
43:           type value_ptr is access value_cell;
3066
44: 
3067
45:           type value_cell is record
3068
46:                                value : bit_vector(0 to 3);
3069
47:                                next_cell : value_ptr;
3070
48:                              end record value_cell;
3071
49: 
3072
50:           variable value_list, cell_to_be_deleted : value_ptr;
3073
51: 
3074

    
3075
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_17_fg_17_05.vhd
3076
ERROR: Parse error at line 43 column 28:
3077

    
3078
33: 
3079
34: 
3080
35: architecture test of fg_17_05 is
3081
36: 
3082
37:   signal s : bit_vector(0 to 3);
3083
38: 
3084
39: begin
3085
40: 
3086
41:   process is
3087
42: 
3088
43:             type value_cell;
3089
                               ^
3090
44: 
3091
45:           type value_ptr is access value_cell;
3092
46: 
3093
47:           type value_cell is record
3094
48:                                value : bit_vector(0 to 3);
3095
49:                                next_cell : value_ptr;
3096
50:                              end record value_cell;
3097
51: 
3098
52:           variable value_list, current_cell : value_ptr;
3099
53: 
3100

    
3101
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_17_fg_17_07.vhd
3102
ERROR: Parse error at line 43 column 28:
3103

    
3104
33: 
3105
34: 
3106
35: architecture test of fg_17_07 is
3107
36: 
3108
37:   signal s : bit_vector(0 to 3);
3109
38: 
3110
39: begin
3111
40: 
3112
41:   process is
3113
42: 
3114
43:             type value_cell;
3115
                               ^
3116
44: 
3117
45:           type value_ptr is access value_cell;
3118
46: 
3119
47:           type value_cell is record
3120
48:                                value : bit_vector(0 to 3);
3121
49:                                next_cell : value_ptr;
3122
50:                              end record value_cell;
3123
51: 
3124
52:           variable value_list, current_cell : value_ptr;
3125
53:           variable search_value : bit_vector(0 to 3);
3126

    
3127
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_17_fg_17_08.vhd
3128
ERROR: Parse error at line 31 column 29:
3129

    
3130
21: --
3131
22: -- $Id: ch_17_fg_17_08.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
3132
23: -- $Revision: 1.2 $
3133
24: --
3134
25: -- ---------------------------------------------------------------------
3135
26: 
3136
27: package bounded_buffer_adt is
3137
28: 
3138
29:   subtype byte is bit_vector(0 to 7);
3139
30: 
3140
31:   type bounded_buffer_object;  -- private
3141
                                ^
3142
32: 
3143
33:   type bounded_buffer is access bounded_buffer_object;
3144
34: 
3145
35:   function new_bounded_buffer ( size : in positive ) return bounded_buffer;
3146
36:   -- creates a bounded buffer object with 'size' bytes of storage
3147
37: 
3148
38:   procedure test_empty ( variable the_bounded_buffer : in bounded_buffer;
3149
39:                          is_empty : out boolean );
3150
40:   -- tests whether the bounded buffer is empty (i.e., no data to read)
3151
41: 
3152

    
3153
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_17_fg_17_11.vhd
3154
ERROR: Parse error at line 31 column 12:
3155

    
3156
21: --
3157
22: -- $Id: ch_17_fg_17_11.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
3158
23: -- $Revision: 1.2 $
3159
24: --
3160
25: -- ---------------------------------------------------------------------
3161
26: 
3162
27: package body bounded_buffer_adt is
3163
28: 
3164
29:   function new_bounded_buffer ( size : in positive ) return bounded_buffer is
3165
30:   begin
3166
31:     return new bounded_buffer_object'(
3167
               ^
3168
32:       byte_count => 0, head_index => 0, tail_index => 0,
3169
33:       store => new store_array(0 to size - 1) );
3170
34:   end function new_bounded_buffer;
3171
35: 
3172
36:   procedure test_empty ( variable the_bounded_buffer : in bounded_buffer;
3173
37:                          is_empty : out boolean ) is
3174
38:   begin
3175
39:     is_empty := the_bounded_buffer.byte_count = 0;
3176
40:   end procedure test_empty;
3177
41: 
3178

    
3179
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_18_ch_18_01.vhd
3180
ERROR: Parse error at line 43 column 34:
3181

    
3182
33: 
3183
34: 
3184
35: architecture test of ch_18_01 is
3185
36: begin
3186
37: 
3187
38: 
3188
39:   process is
3189
40: 
3190
41:             -- code from book:
3191
42: 
3192
43:             type integer_file is file of integer;
3193
                                     ^
3194
44: 
3195
45:           file lookup_table_file : integer_file is "lookup-values";
3196
46: 
3197
47:           -- end of code from book
3198
48: 
3199
49:   begin
3200
50:     wait;
3201
51:   end process;
3202
52: 
3203
53: 
3204

    
3205
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_18_ch_18_02.vhd
3206
ERROR: Parse error at line 35 column 37:
3207

    
3208
25: -- ---------------------------------------------------------------------
3209
26: 
3210
27: entity ch_18_02_a is
3211
28: end entity ch_18_02_a;
3212
29: 
3213
30: 
3214
31: architecture writer of ch_18_02_a is
3215
32: begin
3216
33: 
3217
34:   process is
3218
35:             type bit_vector_file is file of bit_vector;
3219
                                        ^
3220
36:           file vectors : bit_vector_file open write_mode is "vectors.dat";
3221
37:   begin
3222
38:     write(vectors, bit_vector'(""));
3223
39:     write(vectors, bit_vector'("1"));
3224
40:     write(vectors, bit_vector'("10"));
3225
41:     write(vectors, bit_vector'("011"));
3226
42:     write(vectors, bit_vector'("0100"));
3227
43:     write(vectors, bit_vector'("00101"));
3228
44:     write(vectors, bit_vector'("000110"));
3229
45:     write(vectors, bit_vector'("0000111"));
3230

    
3231
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_18_ch_18_03.vhd
3232
ERROR: Parse error at line 43 column 29:
3233

    
3234
33: 
3235
34: 
3236
35: architecture test of ch_18_03 is
3237
36: begin
3238
37: 
3239
38: 
3240
39:   process is
3241
40: 
3242
41:             type element_type is (t1, t2, t3);
3243
42: 
3244
43:           type file_type is file of element_type;
3245
                                ^
3246
44: 
3247
45:           -- code from book:
3248
46: 
3249
47:           procedure write ( file f : file_type;  value : in element_type );
3250
48: 
3251
49:           -- end of code from book
3252
50: 
3253
51:           procedure write ( file f : file_type;  value : in element_type ) is
3254
52:           begin
3255
53:           end;
3256

    
3257
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_18_ch_18_04.vhd
3258
ERROR: Parse error at line 41 column 36:
3259

    
3260
31: 
3261
32: ----------------------------------------------------------------
3262
33: 
3263
34: 
3264
35: architecture test of ch_18_04 is
3265
36: begin
3266
37: 
3267
38: 
3268
39:   process is
3269
40: 
3270
41:             type data_file_type is file of character;
3271
                                       ^
3272
42:           variable ch : character;
3273
43: 
3274
44:           -- code from book:
3275
45: 
3276
46:           procedure write_to_file is
3277
47:             file data_file : data_file_type open write_mode is "datafile";
3278
48:           begin
3279
49:             -- . . .
3280
50:             -- not in book
3281
51:             write(data_file, ch);
3282

    
3283
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_18_ch_18_05.vhd
3284
ERROR: Parse error at line 37 column 20:
3285

    
3286
27: entity ch_18_05 is
3287
28: 
3288
29: end entity ch_18_05;
3289
30: 
3290
31: 
3291
32: ----------------------------------------------------------------
3292
33: 
3293
34: 
3294
35: architecture test of ch_18_05 is
3295
36: 
3296
37:   type log_file is file of string;
3297
                       ^
3298
38: 
3299
39:   -- code from book:
3300
40: 
3301
41:   file log_info : log_file open write_mode is "logfile";
3302
42: 
3303
43:   -- end of code from book
3304
44: 
3305
45: begin
3306
46: 
3307
47: 
3308

    
3309
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_18_ch_18_06.vhd
3310
ERROR: Parse error at line 37 column 24:
3311

    
3312
27: entity ch_18_06 is
3313
28: 
3314
29: end entity ch_18_06;
3315
30: 
3316
31: 
3317
32: ----------------------------------------------------------------
3318
33: 
3319
34: 
3320
35: architecture test of ch_18_06 is
3321
36: 
3322
37:   type integer_file is file of integer;
3323
                           ^
3324
38: 
3325
39: begin
3326
40: 
3327
41: 
3328
42:   process is
3329
43: 
3330
44:             -- code from book:
3331
45: 
3332
46:             file lookup_table_file, result_file : integer_file;
3333
47: 
3334

    
3335
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_18_ch_18_08.vhd
3336
ERROR: Parse error at line 59 column 12:
3337

    
3338
49:   begin
3339
50: 
3340
51:     readline(f, L);
3341
52:     read(L, ch);
3342
53:     report character'image(ch);
3343
54:     read(L, ch);
3344
55:     report character'image(ch);
3345
56: 
3346
57:     readline(f, L);
3347
58:     read(L, s);
3348
59:     report '"' & s & '"';
3349
               ^
3350
60:     read(L, s);
3351
61:     report '"' & s & '"';
3352
62: 
3353
63:     readline(f, L);
3354
64: 
3355
65:     -- code from book:
3356
66: 
3357
67:     if L'length < s'length then
3358
68:       read(L, s(1 to L'length));
3359
69:     else
3360

    
3361
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_18_fg_18_01.vhd
3362
ERROR: Parse error at line 41 column 49:
3363

    
3364
31:                entity fg_18_01_a is
3365
32:                end entity fg_18_01_a;
3366
33: 
3367
34: 
3368
35:                architecture writer of fg_18_01_a is
3369
36:                begin
3370
37: 
3371
38:                  process is
3372
39: 
3373
40:                            subtype word is std_logic_vector(0 to 7);
3374
41:                          type load_file_type is file of word;
3375
                                                    ^
3376
42:                          file load_file : load_file_type open write_mode is "fg_18_01.dat";
3377
43: 
3378
44:                  begin
3379
45:                    write(load_file, word'(X"00"));
3380
46:                    write(load_file, word'(X"01"));
3381
47:                    write(load_file, word'(X"02"));
3382
48:                    write(load_file, word'(X"03"));
3383
49:                    write(load_file, word'(X"04"));
3384
50:                    write(load_file, word'(X"05"));
3385
51:                    write(load_file, word'(X"06"));
3386

    
3387
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_18_fg_18_02.vhd
3388
ERROR: Parse error at line 35 column 33:
3389

    
3390
25: -- ---------------------------------------------------------------------
3391
26: 
3392
27: entity fg_18_02_a is
3393
28: end entity fg_18_02_a;
3394
29: 
3395
30: 
3396
31: architecture writer of fg_18_02_a is
3397
32: begin
3398
33: 
3399
34:   process is
3400
35:             type packet_file is file of bit_vector;
3401
                                    ^
3402
36:           file stimulus_file : packet_file open write_mode is "test packets";
3403
37:   begin
3404
38:     write(stimulus_file, X"6C");
3405
39:     write(stimulus_file, X"05");
3406
40:     write(stimulus_file, X"3");
3407
41: 
3408
42:     wait;
3409
43:   end process;
3410
44: 
3411
45: end architecture writer;
3412

    
3413
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_18_fg_18_03.vhd
3414
ERROR: Parse error at line 35 column 46:
3415

    
3416
25: -- ---------------------------------------------------------------------
3417
26: 
3418
27: library bv_utilities;
3419
28: 
3420
29: package CPU_types is
3421
30: 
3422
31:   subtype word is bit_vector(0 to 31);
3423
32:   subtype byte is bit_vector(0 to 7);
3424
33: 
3425
34:   alias convert_to_natural is
3426
35:     bv_utilities.bv_arithmetic.bv_to_natural [ bit_vector return natural ];
3427
                                                 ^
3428
36: 
3429
37:   constant halt_opcode : byte := "00000000";
3430
38: 
3431
39:   type code_array is array (natural range <>) of word;
3432
40:   constant code : code_array := ( X"01000000", X"01000000", X"02000000",
3433
41:       X"01000000", X"01000000", X"02000000",
3434
42:       X"00000000" );
3435
43: 
3436
44: end package CPU_types;
3437
45: 
3438

    
3439
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_18_fg_18_04.vhd
3440
ERROR: Parse error at line 50 column 52:
3441

    
3442
40: 
3443
41:   cache_monitor : process is
3444
42: 
3445
43:                             type measurement_record is
3446
44:                           record
3447
45:                             cache_size, block_size, associativity : positive;
3448
46:                             benchmark_name : string(1 to 10);
3449
47:                             miss_rate : real;
3450
48:                             ave_access_time : delay_length;
3451
49:                           end record;
3452
50:                           type measurement_file is file of measurement_record;
3453
                                                       ^
3454
51:                           file measurements : measurement_file
3455
52:                             open append_mode is "cache-measurements";
3456
53:                           -- . . .
3457
54: 
3458
55:                           -- not in book
3459
56:                           constant miss_count : natural := 100;
3460
57:                           constant total_accesses : natural := 1000;
3461
58:                           constant total_delay : delay_length := 2400 ns;
3462
59:                           -- end not in book
3463
60: 
3464

    
3465
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_18_fg_18_05.vhd
3466
ERROR: Parse error at line 36 column 34:
3467

    
3468
26: 
3469
27: entity fg_18_05_a is
3470
28: end entity fg_18_05_a;
3471
29: 
3472
30: 
3473
31: architecture writer of fg_18_05_a is
3474
32: begin
3475
33: 
3476
34:   process is
3477
35: 
3478
36:             type integer_file is file of integer;
3479
                                     ^
3480
37:           file data_file : integer_file open write_mode is "coeff-data";
3481
38: 
3482
39:   begin
3483
40:     write(data_file, 0);
3484
41:     write(data_file, 1);
3485
42:     write(data_file, 2);
3486
43:     write(data_file, 3);
3487
44:     write(data_file, 4);
3488
45:     write(data_file, 5);
3489
46:     write(data_file, 6);
3490

    
3491
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_18_fg_18_06.vhd
3492
ERROR: Parse error at line 43 column 72:
3493

    
3494
33:                architecture test of fg_18_06 is
3495
34: 
3496
35: 
3497
36: 
3498
37:                begin
3499
38: 
3500
39:                  -- code from book
3501
40: 
3502
41:                  stimulus_generator : process is
3503
42: 
3504
43:                                                 type directory_file is file of string;
3505
                                                                           ^
3506
44:                                               file directory : directory_file open read_mode is "stimulus-directory";
3507
45:                                               variable file_name : string(1 to 50);
3508
46:                                               variable file_name_length : natural;
3509
47:                                               variable open_status : file_open_status;
3510
48: 
3511
49:                                               subtype stimulus_vector is std_logic_vector(0 to 9);
3512
50:                                               type stimulus_file is file of stimulus_vector;
3513
51:                                               file stimuli : stimulus_file;
3514
52:                                               variable current_stimulus : stimulus_vector;
3515
53:                                               -- . . .
3516

    
3517
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_18_fg_18_07.vhd
3518
ERROR: Parse error at line 35 column 36:
3519

    
3520
25: -- ---------------------------------------------------------------------
3521
26: 
3522
27: entity fg_18_07_a is
3523
28: end entity fg_18_07_a;
3524
29: 
3525
30: 
3526
31: architecture writer of fg_18_07_a is
3527
32: begin
3528
33: 
3529
34:   process is
3530
35:             type transform_file is file of real;
3531
                                       ^
3532
36:           file initial_transforms : transform_file open write_mode is "transforms.ini";
3533
37:   begin
3534
38:     for i in 1 to 50 loop
3535
39:       write(initial_transforms, real(i));
3536
40:     end loop;
3537
41:     wait;
3538
42:   end process;
3539
43: 
3540
44: end architecture writer;
3541
45: 
3542

    
3543
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_18_fg_18_08.vhd
3544
ERROR: Parse error at line 29 column 16:
3545

    
3546
19: 
3547
20: -- ---------------------------------------------------------------------
3548
21: --
3549
22: -- $Id: ch_18_fg_18_08.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
3550
23: -- $Revision: 1.2 $
3551
24: --
3552
25: -- ---------------------------------------------------------------------
3553
26: 
3554
27: package textio is
3555
28: 
3556
29:   type line is access string;
3557
                   ^
3558
30: 
3559
31:   type text is file of string;
3560
32: 
3561
33:   type side is (right, left);
3562
34: 
3563
35:   subtype width is natural;
3564
36: 
3565
37:   file input : text open read_mode is "std_input";
3566
38:   file output : text open write_mode is "std_output";
3567
39: 
3568

    
3569
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_18_fg_18_09.vhd
3570
ERROR: Parse error at line 29 column 35:
3571

    
3572
19: 
3573
20: -- ---------------------------------------------------------------------
3574
21: --
3575
22: -- $Id: ch_18_fg_18_09.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
3576
23: -- $Revision: 1.3 $
3577
24: --
3578
25: -- ---------------------------------------------------------------------
3579
26: 
3580
27: library bv_utilities;
3581
28: 
3582
29: use bv_utilities.bv_arithmetic.all, std.textio.all;
3583
                                      ^
3584
30: 
3585
31: architecture file_loaded of memory is
3586
32: begin
3587
33: 
3588
34:   mem_behavior : process is
3589
35: 
3590
36:                            constant high_address : natural := mem_size - 1;
3591
37: 
3592
38:                          type memory_array is
3593
39:                            array (natural range 0 to high_address / 4) of dlx_bv_word;
3594

    
3595
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_18_fg_18_10.vhd
3596
ERROR: Parse error at line 65 column 9:
3597

    
3598
55: 
3599
56:     command_loop : while not endfile(control) loop
3600
57: 
3601
58:       readline ( control, command );
3602
59: 
3603
60:       -- read next stimulus time, and suspend until then
3604
61:       read ( command, next_time, read_ok );
3605
62:       if not read_ok then
3606
63:         report "error reading time from line: " & command.all
3607
64:           severity warning;
3608
65:         next command_loop;
3609
            ^
3610
66:       end if;
3611
67:       wait for next_time - now;
3612
68: 
3613
69:       -- skip whitespace
3614
70:       while command'length > 0
3615
71:         and ( command(command'left) = ' '    -- ordinary space
3616
72:               or command(command'left) = ' '  -- non-breaking space
3617
73:               or command(command'left) = HT ) loop
3618
74:         read ( command, whitespace );
3619
75:       end loop;
3620

    
3621
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_19_ds-qn.vhd
3622
ERROR: Parse error at line 29 column 24:
3623

    
3624
19: 
3625
20: -- ---------------------------------------------------------------------
3626
21: --
3627
22: -- $Id: ch_19_ds-qn.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
3628
23: -- $Revision: 1.3 $
3629
24: --
3630
25: -- ---------------------------------------------------------------------
3631
26: 
3632
27: library qsim;
3633
28: 
3634
29: use qsim.qsim_types.all, random.random.all;
3635
                           ^
3636
30: 
3637
31: architecture queue_net of disk_system is
3638
32: 
3639
33:   constant disk_cache_miss_rate : real := 0.2;
3640
34:   constant num_disks : positive := 2;
3641
35: 
3642
36:   constant disk_cache_fork_probabilities : probability_vector(1 to num_disks)
3643
37:     := ( others => disk_cache_miss_rate / real(num_disks) );
3644
38: 
3645
39:   signal info_detail_control : info_detail_type := none;
3646

    
3647
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_19_fork.vhd
3648
ERROR: Parse error at line 30 column 24:
3649

    
3650
20: -- ---------------------------------------------------------------------
3651
21: --
3652
22: -- $Id: ch_19_fork.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
3653
23: -- $Revision: 1.3 $
3654
24: --
3655
25: -- ---------------------------------------------------------------------
3656
26: 
3657
27: library qsim;
3658
28: library random;
3659
29: 
3660
30: use qsim.qsim_types.all, random.random.all;
3661
                           ^
3662
31: 
3663
32: entity fork is
3664
33: 
3665
34:   generic ( name : string;
3666
35:             probabilities : probability_vector;
3667
36:             -- must be one element shorter than out_arc port
3668
37:             seed : seed_type;
3669
38:             time_unit : delay_length := ns;
3670
39:             info_file_name : string := "info_file.dat" );
3671
40: 
3672

    
3673
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_19_join-b.vhd
3674
ERROR: Parse error at line 125 column 65:
3675

    
3676
115:     loop
3677
116:       wait on info_detail'transaction, in_arc;
3678
117:       if info_detail'active and info_detail = summary then
3679
118:         write_summary;
3680
119:       end if;
3681
120:       if in_arc'event then
3682
121:  accept_new_tokens;
3683
122:         while current_fifo_size > 0 loop
3684
123:           remove(token_fifo, head_token);
3685
124:           current_fifo_size := current_fifo_size - 1;
3686
125:    out_arc <= arc_type'( transaction => not out_arc.transaction'driving_value,
3687
                                                                     ^
3688
126:            token => head_token );
3689
127:           wait for 0 fs;  -- delta delay before next output token
3690
128:           if info_detail'active and info_detail = summary then
3691
129:             write_summary;
3692
130:           end if;
3693
131:           if in_arc'event then
3694
132:      accept_new_tokens;
3695
133:    end if;
3696
134:         end loop;
3697
135:       end if;
3698

    
3699
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_19_qsimt-b.vhd
3700
ERROR: Parse error at line 37 column 30:
3701

    
3702
27: package body qsim_types is
3703
28: 
3704
29:   use std.textio.all;
3705
30: 
3706
31:   procedure write ( L : inout line;  t : in token_type;
3707
32:   creation_time_unit : in time := ns ) is
3708
33:   begin
3709
34:     write(L, string'("token "));
3710
35:     write(L, natural(t.id));
3711
36:     write(L, string'(" from "));
3712
37:     write(L, t.source_name(1 to t.source_name_length));
3713
                                 ^
3714
38:     write(L, string'(" created at "));
3715
39:     write(L, t.creation_time, unit => creation_time_unit);
3716
40:   end write;
3717
41: 
3718
42: end package body qsim_types;
3719
43: 
3720

    
3721
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_19_qsimt.vhd
3722
ERROR: Parse error at line 33 column 48:
3723

    
3724
23: -- $Revision: 1.2 $
3725
24: --
3726
25: -- ---------------------------------------------------------------------
3727
26: 
3728
27: --use std.textio.line;
3729
28: use std.textio.all;
3730
29: 
3731
30: package qsim_types is
3732
31: 
3733
32:   constant name_max_length : natural := 20;
3734
33:   type token_id_type is range 0 to integer'high;
3735
                                                   ^
3736
34: 
3737
35:   type token_type is record
3738
36:                        source_name : string(1 to name_max_length);
3739
37:                        source_name_length : natural;
3740
38:                        id : token_id_type;
3741
39:                        creation_time : time;
3742
40:                      end record;
3743
41: 
3744
42:   type token_vector is array (positive range <>) of token_type;
3745
43: 
3746

    
3747
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_19_queue-b.vhd
3748
ERROR: Parse error at line 35 column 53:
3749

    
3750
25: -- ---------------------------------------------------------------------
3751
26: 
3752
27: library math;
3753
28: 
3754
29: architecture behavior of queue is
3755
30: 
3756
31: begin
3757
32: 
3758
33:   queue_manager : process is
3759
34: 
3760
35:                             use qsim.queue_types.all, qsim.waiting_token_fifo_adt.all;
3761
                                                        ^
3762
36: 
3763
37:                           variable waiting_token, head_token : waiting_token_type;
3764
38:                           variable waiting_token_fifo : fifo_type := new_fifo;
3765
39:                           variable out_token_in_transit : boolean := false;
3766
40:                           variable number_of_tokens_released : natural := 0;
3767
41:                           variable current_queue_size : natural := 0;
3768
42:                           variable maximum_queue_size : natural := 0;
3769
43:                           variable waiting_time : natural;  -- in time_unit
3770
44:                           variable sum_of_waiting_times : real := 0.0;  -- in time_unit
3771
45:                           variable sum_of_squares_of_waiting_times : real := 0.0;  --in time_unit**2
3772

    
3773
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_19_random-b.vhd
3774
ERROR: Parse error at line 124 column 75:
3775

    
3776
114:     random_info.distribution := exponential;
3777
115:     random_info.mean := mean;
3778
116:     random_info.seed := seed;
3779
117:   end procedure init_exponential;
3780
118: 
3781
119: 
3782
120:   procedure generate_uniform ( random_info : inout random_info_record;
3783
121:                                random_number : out real ) is
3784
122:     variable tmp : real;
3785
123:   begin
3786
124:     math_real.uniform(random_info.seed.seed1, random_info.seed.seed2, tmp);
3787
                                                                               ^
3788
125:     random_number := random_info.lower_bound
3789
126:                      + tmp * (random_info.upper_bound - random_info.lower_bound);
3790
127:   end procedure generate_uniform;
3791
128: 
3792
129: 
3793
130:   procedure generate_exponential ( random_info : inout random_info_record;
3794
131:                                    random_number : out real ) is
3795
132:     variable tmp : real;
3796
133:   begin
3797
134:     loop
3798

    
3799
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_19_source-b.vhd
3800
ERROR: Parse error at line 129 column 68:
3801

    
3802
119:       generate_random(random_info, random_number);
3803
120:       inter_arrival_time :=  natural(random_number);
3804
121:       next_arrival_time := inter_arrival_time * time_unit + now;
3805
122:       loop
3806
123:         wait on info_detail'transaction for next_arrival_time - now;
3807
124:         if info_detail'active and info_detail = summary then
3808
125:           write_summary;
3809
126:         end if;
3810
127:         exit when next_arrival_time = now;
3811
128:       end loop;
3812
129:       out_arc <= arc_type'( transaction => not out_arc.transaction'driving_value,
3813
                                                                        ^
3814
130:               token => token_type'( source_name => source_name,
3815
131:                                                   source_name_length => source_name_length,
3816
132:                                                   id => next_token_id,
3817
133:                                                   creation_time => now ) );
3818
134:       number_of_tokens_generated := number_of_tokens_generated + 1;
3819
135:       sum_of_inter_arrival_times := sum_of_inter_arrival_times
3820
136:                                     + real(inter_arrival_time);
3821
137:       sum_of_squares_of_inter_arrival_times := sum_of_squares_of_inter_arrival_times
3822
138:                                                + real(inter_arrival_time) ** 2;
3823
139: 
3824

    
3825
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_19_source.vhd
3826
ERROR: Parse error at line 30 column 24:
3827

    
3828
20: -- ---------------------------------------------------------------------
3829
21: --
3830
22: -- $Id: ch_19_source.vhd,v 1.2 2001-10-24 22:18:13 paw Exp $
3831
23: -- $Revision: 1.2 $
3832
24: --
3833
25: -- ---------------------------------------------------------------------
3834
26: 
3835
27: library qsim;
3836
28: library random;
3837
29: 
3838
30: use qsim.qsim_types.all, random.random.all;
3839
                           ^
3840
31: 
3841
32: entity source is
3842
33: 
3843
34:   generic ( name : string;
3844
35:             distribution : distribution_type;
3845
36:             mean_inter_arrival_time : delay_length;
3846
37:             seed : seed_type;
3847
38:             time_unit : delay_length := ns;
3848
39:             info_file_name : string := "info_file.dat" );
3849
40: 
3850

    
3851
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_19_srvr-b.vhd
3852
ERROR: Parse error at line 146 column 63:
3853

    
3854
136:         service_time :=  natural(random_number);
3855
137:         release_time := service_time * time_unit + now;
3856
138:         loop
3857
139:           wait on info_detail'transaction for release_time - now;
3858
140:           if info_detail'active and info_detail = summary then
3859
141:             write_summary;
3860
142:           end if;
3861
143:           exit when release_time = now;
3862
144:         end loop;
3863
145:  in_ready <= true;
3864
146:  out_arc <= arc_type'( transaction => not out_arc.transaction'driving_value,
3865
                                                                   ^
3866
147:          token => served_token );
3867
148:         number_of_tokens_served := number_of_tokens_served + 1;
3868
149:         sum_of_service_times := sum_of_service_times + real(service_time);
3869
150:         sum_of_squares_of_service_times := sum_of_squares_of_service_times
3870
151:                                            + real(service_time) ** 2;
3871
152:         if info_detail = trace then
3872
153:           write_trace_release;
3873
154:         end if;
3874
155:       end if;
3875
156:     end loop;
3876

    
3877
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_19_srvr.vhd
3878
ERROR: Parse error at line 30 column 26:
3879

    
3880
20: -- ---------------------------------------------------------------------
3881
21: --
3882
22: -- $Id: ch_19_srvr.vhd,v 1.5 2001-10-26 16:29:36 paw Exp $
3883
23: -- $Revision: 1.5 $
3884
24: --
3885
25: -- ---------------------------------------------------------------------
3886
26: 
3887
27: library qsim;
3888
28: library random;
3889
29: 
3890
30:   use qsim.qsim_types.all, random.random.all;
3891
                             ^
3892
31: 
3893
32: entity server is
3894
33: 
3895
34:   generic ( name : string;
3896
35:             distribution : distribution_type;
3897
36:             mean_service_time : time;
3898
37:             seed : seed_type;
3899
38:             time_unit : delay_length := ns;
3900
39:             info_file_name : string := "info_file.dat" );
3901
40: 
3902

    
3903
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_19_tkfifo-b.vhd
3904
ERROR: Parse error at line 31 column 12:
3905

    
3906
21: --
3907
22: -- $Id: ch_19_tkfifo-b.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
3908
23: -- $Revision: 1.3 $
3909
24: --
3910
25: -- ---------------------------------------------------------------------
3911
26: 
3912
27: package body token_fifo_adt is
3913
28: 
3914
29:   function new_fifo return fifo_type is
3915
30:   begin
3916
31:     return new fifo_record'( null, null );
3917
               ^
3918
32:   end function new_fifo;
3919
33: 
3920
34: 
3921
35:   procedure test_empty ( variable fifo : in fifo_type;
3922
36:                          variable is_empty : out boolean ) is
3923
37:   begin
3924
38:     is_empty := fifo.head_entry = null;
3925
39:   end procedure test_empty;
3926
40: 
3927
41: 
3928

    
3929
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_19_tkfifo.vhd
3930
ERROR: Parse error at line 33 column 19:
3931

    
3932
23: -- $Revision: 1.3 $
3933
24: --
3934
25: -- ---------------------------------------------------------------------
3935
26: 
3936
27: library qsim;
3937
28: 
3938
29: package token_fifo_adt is
3939
30: 
3940
31:   alias element_type is qsim.qsim_types.token_type;
3941
32: 
3942
33:   type fifo_record;
3943
                      ^
3944
34: 
3945
35:   type fifo_type is access fifo_record;
3946
36: 
3947
37:   function new_fifo return fifo_type;
3948
38: 
3949
39:   procedure test_empty ( variable fifo : in fifo_type;
3950
40:                          variable is_empty : out boolean );
3951
41: 
3952
42:   procedure insert ( fifo : inout fifo_type;
3953
43:                      element : in element_type );
3954

    
3955
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_19_wtfifo-b.vhd
3956
ERROR: Parse error at line 31 column 12:
3957

    
3958
21: --
3959
22: -- $Id: ch_19_wtfifo-b.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
3960
23: -- $Revision: 1.3 $
3961
24: --
3962
25: -- ---------------------------------------------------------------------
3963
26: 
3964
27: package body waiting_token_fifo_adt is
3965
28: 
3966
29:   function new_fifo return fifo_type is
3967
30:   begin
3968
31:     return new fifo_record'( null, null );
3969
               ^
3970
32:   end function new_fifo;
3971
33: 
3972
34: 
3973
35:   procedure test_empty ( variable fifo : in fifo_type;
3974
36:                          variable is_empty : out boolean ) is
3975
37:   begin
3976
38:     is_empty := fifo.head_entry = null;
3977
39:   end procedure test_empty;
3978
40: 
3979
41: 
3980

    
3981
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_19_wtfifo.vhd
3982
ERROR: Parse error at line 33 column 19:
3983

    
3984
23: -- $Revision: 1.3 $
3985
24: --
3986
25: -- ---------------------------------------------------------------------
3987
26: 
3988
27: library qsim;
3989
28: 
3990
29: package waiting_token_fifo_adt is
3991
30: 
3992
31:   alias element_type is qsim.queue_types.waiting_token_type;
3993
32: 
3994
33:   type fifo_record;
3995
                      ^
3996
34: 
3997
35:   type fifo_type is access fifo_record;
3998
36: 
3999
37:   function new_fifo return fifo_type;
4000
38: 
4001
39:   procedure test_empty ( variable fifo : in fifo_type;
4002
40:                          variable is_empty : out boolean );
4003
41: 
4004
42:   procedure insert ( fifo : inout fifo_type;
4005
43:                      element : in element_type );
4006

    
4007
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_20_ch_20_01.vhd
4008
ERROR: Parse error at line 58 column 47:
4009

    
4010
48: begin
4011
49: 
4012
50: 
4013
51:   process is
4014
52:   begin
4015
53: 
4016
54:     report
4017
55: 
4018
56:       -- code from book:
4019
57: 
4020
58:       utilities.utility_definitions.word_size'simple_name
4021
                                                  ^
4022
59: 
4023
60:       -- end of code from book
4024
61: 
4025
62:       ;
4026
63: 
4027
64:     wait;
4028
65:   end process;
4029
66: 
4030
67: 
4031
68: end architecture test;
4032

    
4033
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_20_ch_20_03.vhd
4034
ERROR: Parse error at line 38 column 13:
4035

    
4036
28: 
4037
29:   -- code from book:
4038
30: 
4039
31:   attribute cell_name : string;
4040
32:   attribute pin_number : positive;
4041
33:   attribute max_wire_delay : delay_length;
4042
34:   attribute encoding : bit_vector;
4043
35: 
4044
36: 
4045
37:   type length is range 0 to integer'high
4046
38:     units nm;
4047
                ^
4048
39:           um = 1000 nm;
4049
40:           mm = 1000 um;
4050
41:           mil = 25400 nm;
4051
42:     end units length;
4052
43: 
4053
44:   type coordinate is record
4054
45:                        x, y : length;
4055
46:                      end record coordinate;
4056
47: 
4057
48:   attribute cell_position : coordinate;
4058

    
4059
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_20_ch_20_05.vhd
4060
ERROR: Parse error at line 45 column 9:
4061

    
4062
35: architecture test of ch_20_05 is
4063
36: 
4064
37:   type stimulus_list is array (natural range <>) of integer;
4065
38: 
4066
39:   -- code from book:
4067
40: 
4068
41:   function "&" ( a, b : stimulus_list ) return stimulus_list;
4069
42: 
4070
43:   attribute debug : string;
4071
44:   attribute debug of
4072
45:     "&" [ stimulus_list, stimulus_list return stimulus_list ] : function is
4073
            ^
4074
46:     "source_statement_step";
4075
47: 
4076
48: 
4077
49:     type mvl is ('X', '0', '1', 'Z');
4078
50:     type mvl_vector is array ( integer range <>) of mvl;
4079
51:     function resolve_mvl ( drivers : mvl_vector ) return mvl;
4080
52: 
4081
53:     subtype resolved_mvl is resolve_mvl mvl;
4082
54: 
4083
55: 
4084

    
4085
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_20_ch_20_06.vhd
4086
ERROR: Parse error at line 51 column 49:
4087

    
4088
41: begin
4089
42: 
4090
43: 
4091
44:   process1 : process is
4092
45: 
4093
46:                        -- code from book:
4094
47: 
4095
48:                        type controller_state is (idle, active, fail_safe);
4096
49:                      type load_level is (idle, busy, overloaded);
4097
50: 
4098
51:                      attribute encoding of idle [ return controller_state ] : literal is b"00";
4099
                                                    ^
4100
52:                                                                                          attribute encoding of active [ return controller_state ] : literal is b"01";
4101
53:                                                                                                                                                                attribute encoding of fail_safe [ return controller_state ] : literal is b"10";
4102
54: 
4103
55:                                                                                                                                                                                                                                         -- end of code from book
4104
56: 
4105
57:                                                                                                                                                                                                                                         variable L : line;
4106
58: 
4107
59:                                                                                                                                                                begin
4108
60:                                                                                                                                                                  write(L, string'("process1"));
4109
61:                                                                                                                                                                  writeline(output, L);
4110

    
4111
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_20_ch_20_07.vhd
4112
ERROR: Parse error at line 41 column 13:
4113

    
4114
31: 
4115
32: ----------------------------------------------------------------
4116
33: 
4117
34: 
4118
35: architecture test of ch_20_07 is
4119
36: 
4120
37:   component multiplier is
4121
38:   end component multiplier;
4122
39: 
4123
40:   type length is range 0 to integer'high
4124
41:     units nm;
4125
                ^
4126
42:           um = 1000 nm;
4127
43:           mm = 1000 um;
4128
44:           mil = 25400 nm;
4129
45:     end units length;
4130
46: 
4131
47:   type coordinate is record
4132
48:                        x, y : length;
4133
49:                      end record coordinate;
4134
50: 
4135
51:   type orientation_type is (up, down, left, right);
4136

    
4137
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_20_ch_20_08.vhd
4138
ERROR: Parse error at line 45 column 13:
4139

    
4140
35: library ieee;  use ieee.std_logic_1164.all;
4141
36: 
4142
37: architecture std_cell of ch_20_08 is
4143
38: 
4144
39:   attribute cell_name : string;
4145
40:   attribute pin_number : positive;
4146
41:   attribute max_wire_delay : delay_length;
4147
42:   attribute encoding : bit_vector;
4148
43: 
4149
44:   type length is range 0 to integer'high
4150
45:     units nm;
4151
                ^
4152
46:           um = 1000 nm;
4153
47:           mm = 1000 um;
4154
48:           mil = 25400 nm;
4155
49:     end units length;
4156
50: 
4157
51:   type coordinate is record
4158
52:                        x, y : length;
4159
53:                      end record coordinate;
4160
54: 
4161
55:   attribute cell_position : coordinate;
4162

    
4163
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_20_ch_20_11.vhd
4164
ERROR: Parse error at line 44 column 3:
4165

    
4166
34: 
4167
35: architecture test of ch_20_11 is
4168
36: 
4169
37:   component comp is
4170
38:   end component comp;
4171
39: 
4172
40:   signal clk_phase1, clk_phase2 : bit;
4173
41: 
4174
42:   -- code from book:
4175
43: 
4176
44:   group signal_pair is (signal, signal);
4177
      ^
4178
45: 
4179
46:   group clock_pair : signal_pair ( clk_phase1, clk_phase2 );
4180
47: 
4181
48:   attribute max_skew : time;
4182
49: 
4183
50:   attribute max_skew of clock_pair : group is 200 ps;
4184
51: 
4185
52:   group component_instances is ( label <> );
4186
53: 
4187
54:   group U1 : component_instances ( nand1, nand2, nand3 );
4188

    
4189
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_20_fg_20_09.vhd
4190
ERROR: Parse error at line 61 column 12:
4191

    
4192
51:   begin
4193
52:     -- . . .
4194
53:     --
4195
54:     report "--6: " & v'path_name;
4196
55:     report "--6: " & v'instance_name;
4197
56:     --
4198
57:   end procedure proc;
4199
58: 
4200
59: begin
4201
60: 
4202
61:   delays : block is
4203
               ^
4204
62:                    constant d : integer := 1;      -- 7
4205
63:   begin
4206
64:     -- . . .
4207
65:     --
4208
66:     assert false report "--7: " & d'path_name;
4209
67:     assert false report "--7: " & d'instance_name;
4210
68:     --
4211
69:   end block delays;
4212
70: 
4213
71:   func : block is
4214

    
4215
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_20_fg_20_11.vhd
4216
ERROR: Parse error at line 59 column 23:
4217

    
4218
49:                                 overflow : out boolean ) is -- . . .
4219
50: 
4220
51:     -- not in book
4221
52:   begin
4222
53:   end;
4223
54:   -- end not in book
4224
55: 
4225
56:   attribute built_in : string;
4226
57: 
4227
58:   attribute built_in of
4228
59:     add_with_overflow [ integer, integer,
4229
                          ^
4230
60:                         integer, boolean ] : procedure is "int_add_overflow";
4231
61: 
4232
62:   attribute built_in of
4233
63:     add_with_overflow [ bit_vector, bit_vector,
4234
64:                         bit_vector, boolean ] : procedure is "bit_vector_add_overflow";
4235
65: 
4236
66:   begin
4237
67:     -- . . .
4238
68:     -- not in book
4239
69:     wait;
4240

    
4241
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_20_fg_20_12.vhd
4242
ERROR: Parse error at line 44 column 8:
4243

    
4244
34:   -- end code from book
4245
35: 
4246
36: end package physical_attributes;
4247
37: 
4248
38: 
4249
39: -- code from book
4250
40: 
4251
41: library ieee;  use ieee.std_logic_1164.all;
4252
42: use work.physical_attributes.all;
4253
43: 
4254
44: entity \74x138\ is
4255
           ^
4256
45:   generic ( Tpd : time );
4257
46:   port ( en1, en2a_n, en2b_n : in std_logic;
4258
47:          s0, s1, s2 : in std_logic;
4259
48:          y0, y1, y2, y3, y4, y5, y6, y7 : out std_logic );
4260
49: 
4261
50:   attribute layout_ignore of Tpd : constant is true;
4262
51: 
4263
52:   attribute pin_number of s0 : signal is 1;
4264
53:   attribute pin_number of s1 : signal is 2;
4265
54:   attribute pin_number of s2 : signal is 3;
4266

    
4267
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_20_fg_20_15.vhd
4268
ERROR: Parse error at line 30 column 13:
4269

    
4270
20: -- ---------------------------------------------------------------------
4271
21: --
4272
22: -- $Id: ch_20_fg_20_15.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
4273
23: -- $Revision: 1.2 $
4274
24: --
4275
25: -- ---------------------------------------------------------------------
4276
26: 
4277
27: package cell_attributes is
4278
28: 
4279
29:   type length is range 0 to integer'high
4280
30:     units nm;
4281
                ^
4282
31:           um = 1000 nm;
4283
32:           mm = 1000 um;
4284
33:           mil = 25400 nm;
4285
34:     end units length;
4286
35: 
4287
36:   type coordinate is record
4288
37:                        x, y : length;
4289
38:                      end record coordinate;
4290
39: 
4291
40:   attribute cell_position : coordinate;
4292

    
4293
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_20_fg_20_17.vhd
4294
ERROR: Parse error at line 31 column 9:
4295

    
4296
21: --
4297
22: -- $Id: ch_20_fg_20_17.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
4298
23: -- $Revision: 1.2 $
4299
24: --
4300
25: -- ---------------------------------------------------------------------
4301
26: 
4302
27: package voltage_defs is
4303
28: 
4304
29:   type voltage is range -2e9 to +2e9
4305
30:     units
4306
31:       nV;
4307
            ^
4308
32:       uV = 1000 nV;
4309
33:       mV = 1000 uV;
4310
34:       V = 1000 mV;
4311
35:     end units voltage;
4312
36: 
4313
37:   attribute resolution : real;
4314
38: 
4315
39:   attribute resolution of nV : units is 1.0;
4316
40:                                      attribute resolution of uV : units is 0.01;
4317
41:                                                                         attribute resolution of mV : units is 0.01;
4318

    
4319
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_20_fg_20_20.vhd
4320
ERROR: Parse error at line 31 column 3:
4321

    
4322
21: --
4323
22: -- $Id: ch_20_fg_20_20.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
4324
23: -- $Revision: 1.1.1.1 $
4325
24: --
4326
25: -- ---------------------------------------------------------------------
4327
26: 
4328
27: package constraints is
4329
28: 
4330
29:   -- code from book (in text)
4331
30: 
4332
31:   group port_pair is ( signal, signal );
4333
      ^
4334
32: 
4335
33:   attribute max_prop_delay : time;
4336
34: 
4337
35:   -- end code from book
4338
36: 
4339
37: end package constraints;
4340
38: 
4341
39: 
4342
40: 
4343
41: -- code from book
4344

    
4345
ERROR: Unable to parse source file : /home/adieumeg/Documents/Projects/Valencia/workspaces/vhdl_examples/ghdl/ghdl/testsuite/vests/vhdl-93/ashenden/compliant/parse_error/ch_21_fg_21_02.vhd
4346
ERROR: Parse error at line 49 column 66:
4347

    
4348
39:                end package project_util;
4349
40: 
4350
41: 
4351
42:                package body project_util is
4352
43: 
4353
44:                  function "<" ( bv1, bv2 : bit_vector ) return boolean is
4354
45:                    variable tmp1 : bit_vector(bv1'range) := bv1;
4355
46:                    variable tmp2 : bit_vector(bv2'range) := bv2;
4356
47:                  begin
4357
48:                    assert bv1'length = bv2'length
4358
49:                      report "vectors are of different length in ""<"" comparison"
4359
                                                                     ^
4360
50:                      severity failure;
4361
51:                    tmp1(tmp1'left) := not tmp1(tmp1'left);
4362
52:                    tmp2(tmp2'left) := not tmp2(tmp2'left);
4363
53:                    return std.standard."<" ( tmp1, tmp2 );
4364
54:                  end function "<";
4365
55: 
4366
56:                end package body project_util;
4367
57: 
4368
58: 
4369
59: 
4370

    
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