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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_20_fg_20_20.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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package constraints is
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  -- code from book (in text)
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  group port_pair is ( signal, signal );
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  attribute max_prop_delay : time;
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  -- end code from book
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end package constraints;
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-- code from book
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library ieee;  use ieee.std_logic_1164.all;
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use work.constraints.port_pair, work.constraints.max_prop_delay;
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entity clock_buffer is
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  port ( clock_in : in std_logic;
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         clock_out1, clock_out2, clock_out3 : out std_logic );
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  group clock_to_out1 : port_pair ( clock_in, clock_out1 );
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  group clock_to_out2 : port_pair ( clock_in, clock_out2 );
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  group clock_to_out3 : port_pair ( clock_in, clock_out3 );
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  attribute max_prop_delay of clock_to_out1 : group is 2 ns;
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  attribute max_prop_delay of clock_to_out2 : group is 2 ns;
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  attribute max_prop_delay of clock_to_out3 : group is 2 ns;
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end entity clock_buffer;
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-- end code from book
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