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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_20_fg_20_12.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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package physical_attributes is
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  -- code from book (in text)
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  attribute layout_ignore : boolean;
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  attribute pin_number : positive;
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  -- end code from book
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end package physical_attributes;
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-- code from book
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library ieee;  use ieee.std_logic_1164.all;
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use work.physical_attributes.all;
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entity \74x138\ is
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  generic ( Tpd : time );
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  port ( en1, en2a_n, en2b_n : in std_logic;
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         s0, s1, s2 : in std_logic;
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         y0, y1, y2, y3, y4, y5, y6, y7 : out std_logic );
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  attribute layout_ignore of Tpd : constant is true;
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  attribute pin_number of s0 : signal is 1;
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  attribute pin_number of s1 : signal is 2;
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  attribute pin_number of s2 : signal is 3;
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  attribute pin_number of en2a_n : signal is 4;
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  -- . . .
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end entity \74x138\;
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-- code from book
(166-166/171)