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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_20_ch_20_11.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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entity ch_20_11 is
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end entity ch_20_11;
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----------------------------------------------------------------
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architecture test of ch_20_11 is
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  component comp is
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  end component comp;
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  signal clk_phase1, clk_phase2 : bit;
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  -- code from book:
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  group signal_pair is (signal, signal);
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  group clock_pair : signal_pair ( clk_phase1, clk_phase2 );
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  attribute max_skew : time;
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  attribute max_skew of clock_pair : group is 200 ps;
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  group component_instances is ( label <> );
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  group U1 : component_instances ( nand1, nand2, nand3 );
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  group U2 : component_instances ( inv1, inv2 );
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  attribute IC_allocation : string;
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  attribute IC_allocation of U1 : group is "74LS00";
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  attribute IC_allocation of U2 : group is "74LS04";
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  -- end of code from book
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begin
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  nand1 : component comp;
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  nand2 : component comp;
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  nand3 : component comp;
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  inv1 : component comp;
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  inv2 : component comp;
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end architecture test;
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