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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_20_ch_20_03.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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package ch_20_03_a is
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  -- code from book:
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  attribute cell_name : string;
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  attribute pin_number : positive;
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  attribute max_wire_delay : delay_length;
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  attribute encoding : bit_vector;
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  type length is range 0 to integer'high
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    units nm;
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          um = 1000 nm;
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          mm = 1000 um;
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          mil = 25400 nm;
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    end units length;
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  type coordinate is record
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                       x, y : length;
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                     end record coordinate;
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  attribute cell_position : coordinate;
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  -- end of code from book
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end package ch_20_03_a;
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entity ch_20_03 is
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end entity ch_20_03;
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----------------------------------------------------------------
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architecture std_cell of ch_20_03 is
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  use work.ch_20_03_a.all;
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  signal enable, clk : bit;
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  type state_type is (idle_state, other_state);
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  -- code from book:
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  attribute cell_name of std_cell : architecture is "DFF_SR_QQNN";
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  attribute pin_number of enable : signal is 14;
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  attribute max_wire_delay of clk : signal is 50 ps;
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  attribute encoding of idle_state : literal is b"0000";
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  attribute cell_position of the_fpu : label is ( 540 um, 1200 um );
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  -- end of code from book
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begin
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  the_fpu : block is
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  begin
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  end block the_fpu;
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  process is
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            use std.textio.all;
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          variable L : line;
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  begin
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    write(L, std_cell'cell_name);
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    writeline(output, L);
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    write(L, enable'pin_number);
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    writeline(output, L);
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    write(L, clk'max_wire_delay);
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    writeline(output, L);
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    write(L, idle_state[return state_type]'encoding);
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    writeline(output, L);
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    write(L, length'image(the_fpu'cell_position.x));
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    write(L, ' ');
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    write(L, length'image(the_fpu'cell_position.y));
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    writeline(output, L);
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    wait;
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  end process;
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end architecture std_cell;
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