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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_19_qsimt.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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--use std.textio.line;
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use std.textio.all;
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package qsim_types is
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  constant name_max_length : natural := 20;
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  type token_id_type is range 0 to integer'high;
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  type token_type is record
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                       source_name : string(1 to name_max_length);
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                       source_name_length : natural;
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                       id : token_id_type;
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                       creation_time : time;
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                     end record;
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  type token_vector is array (positive range <>) of token_type;
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  type arc_type is record
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                     transaction : boolean;  -- flips when an arc changes
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                     token : token_type;
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                   end record arc_type;
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  type arc_vector is array (positive range <>) of arc_type;
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  type info_detail_type is (none, summary, trace);
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  procedure write ( L : inout line;  t : in token_type;
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  creation_time_unit : in time := ns );
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end package qsim_types;
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