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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_17_fg_17_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity fg_17_05 is
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end entity fg_17_05;
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----------------------------------------------------------------
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architecture test of fg_17_05 is
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  signal s : bit_vector(0 to 3);
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begin
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  process is
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            type value_cell;
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          type value_ptr is access value_cell;
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          type value_cell is record
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                               value : bit_vector(0 to 3);
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                               next_cell : value_ptr;
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                             end record value_cell;
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          variable value_list, current_cell : value_ptr;
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  begin
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    value_list := new value_cell'( B"1000", value_list );
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    value_list := new value_cell'( B"0010", value_list );
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    value_list := new value_cell'( B"0000", value_list );
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    -- code from book:
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    current_cell := value_list;
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    while current_cell /= null loop
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      s <= current_cell.value;
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      wait for 10 ns;
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      current_cell := current_cell.next_cell;
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    end loop;
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    -- end of code from book
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    wait;
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  end process;
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end architecture test;
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