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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_16_fg_16_15.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity circuit is
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  generic ( inpad_delay, outpad_delay : delay_length );
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  port ( in1, in2, in3 : in bit;  out1, out2 : out bit );
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end entity circuit;
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--------------------------------------------------
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architecture with_pad_delays of circuit is
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  component subcircuit is
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                         port ( a, b : in bit;  y1, y2 : out bit );
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  end component subcircuit;
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  signal delayed_in1, delayed_in2, delayed_in3 : bit;
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  signal undelayed_out1, undelayed_out2 : bit;
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begin
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  input_delays : block is
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  begin
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    delayed_in1 <= in1 after inpad_delay;
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    delayed_in2 <= in2 after inpad_delay;
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    delayed_in3 <= in3 after inpad_delay;
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  end block input_delays;
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  functionality : block is
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                          signal intermediate : bit;
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  begin
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    cell1 : component subcircuit
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      port map ( delayed_in1, delayed_in2, undelayed_out1, intermediate );
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    cell2 : component subcircuit
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      port map ( intermediate, delayed_in3, undelayed_out2, open );
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  end block functionality;
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  output_delays : block is
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  begin
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    out1 <= undelayed_out1 after outpad_delay;
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    out2 <= undelayed_out2 after outpad_delay;
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  end block output_delays;
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end architecture with_pad_delays;
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