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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_16_fg_16_07.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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library ieee;  use ieee.std_logic_1164.all;
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               entity fg_16_07 is
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               end entity fg_16_07;
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               architecture test of fg_16_07 is
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                 constant reg0 : std_logic_vector(7 downto 0) := "00000000";
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                 constant reg1 : std_logic_vector(7 downto 0) := "11111111";
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                 signal dbus : std_logic_vector(7 downto 0);
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                 signal reg_sel, read, reg_addr : X01 := '0';
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               begin
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                 -- code from book
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                 reg_read_selector : block (reg_sel = '1' and read = '1') is
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                 begin
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                   dbus <= reg0 when guard and reg_addr = '0' else
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                           reg1 when guard and reg_addr = '1' else
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                           "ZZZZZZZZ";
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                 end block reg_read_selector;
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                 -- end code from book
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                 stimulus : process is
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                 begin
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                   reg_sel <= '1';  wait for 10 ns;
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                   read <= '1', '0' after 5 ns;  wait for 10 ns;
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                   reg_sel <= '0';  wait for 10 ns;
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                   read <= '1', '0' after 5 ns;  wait for 10 ns;
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                   reg_addr <= '1';  wait for 10 ns;
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                   reg_sel <= '1';  wait for 10 ns;
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                   read <= '1', '0' after 5 ns;  wait for 10 ns;
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                   wait;
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                 end process stimulus;
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               end architecture test;
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