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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_16_fg_16_05.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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use work.fg_16_04.all;
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-- code from book (in text)
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entity tri_state_reg is
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  port ( d : in resolved_byte;
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         q : out resolved_byte bus;
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         clock, out_enable : in bit );
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end entity tri_state_reg;
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-- end code from book
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-- code from book
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architecture behavioral of tri_state_reg is
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begin
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  reg_behavior : process (d, clock, out_enable) is
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                                                  variable stored_byte : byte;
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  begin
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    if clock'event and clock = '1' then
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      stored_byte := d;
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    end if;
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    if out_enable = '1' then
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      q <= stored_byte;
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    else
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      q <= null;
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    end if;
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  end process reg_behavior;
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end architecture behavioral;
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-- end code from book
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use work.fg_16_04.all;
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entity fg_16_05 is
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end entity fg_16_05;
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architecture test of fg_16_05 is
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  signal d1, d2, q : resolved_byte := X"00";
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  signal clk1, clk2, oe1, oe2 : bit := '0';
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begin
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  dut1 : entity work.tri_state_reg(behavioral)
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    port map ( d => d1, q => q, clock => clk1, out_enable => oe1 );
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  dut2 : entity work.tri_state_reg(behavioral)
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    port map ( d => d2, q => q, clock => clk2, out_enable => oe2 );
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  stimulus : process is
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  begin
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    d1 <= X"11";  clk1 <= '1', '0' after 5 ns;  wait for 10 ns;
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    oe1 <= '1', '0' after 5 ns;  wait for 10 ns;
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    d2 <= X"21";  clk2 <= '1', '0' after 5 ns;  wait for 10 ns;
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    oe2 <= '1', '0' after 5 ns;  wait for 10 ns;
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    oe1 <= '1', '0' after 5 ns;
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    oe2 <= '1', '0' after 5 ns;
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    wait;
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  end process stimulus;
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end architecture test;
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