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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_16_fg_16_02.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity processor is
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end entity processor;
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-- code from book
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architecture rtl of processor is
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  subtype word is bit_vector(0 to 31);
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  type word_vector is array (natural range <>) of word;
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  function resolve_unique ( drivers : word_vector ) return word is
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  begin
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    return drivers(drivers'left);
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  end function resolve_unique;
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  signal source1, source2 : resolve_unique word register;
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  -- . . .
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  -- not in book
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  type alu_op_type is (pass1, pass2, add, subtract);
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  procedure perform_alu_op ( signal alu_opcode : in alu_op_type;
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			     signal source1, source2 : in word;
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			     signal destination : out word;
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			     constant ignored : in integer := 0 ) is
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  begin
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    null;
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  end procedure perform_alu_op;
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  signal phase1, source1_reg_out_en,other_signal : bit;
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  signal alu_opcode : alu_op_type;
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  signal destination : word;
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  -- end not in book
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begin
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  source1_reg : process (phase1, source1_reg_out_en, -- . . .) is
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                         -- not in book
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                         other_signal) is
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                                         -- end not in book
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                                         variable stored_value : word;
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  begin
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    -- . . .
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    if source1_reg_out_en = '1' and phase1 = '1' then
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      source1 <= stored_value;
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      -- not in book
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      stored_value := not stored_value;
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      -- end not in book
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    else
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      source1 <= null;
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    end if;
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  end process source1_reg;
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  alu : perform_alu_op ( alu_opcode, source1, source2, destination, -- . . . );
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                         -- not in book
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                         open );
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  -- end not in book
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  -- . . .
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  -- not in book
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  process is
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  begin
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    wait for 10 ns;
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    source1_reg_out_en <= '1';
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    phase1 <= '1', '0' after 10 ns;
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    wait for 20 ns;
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    source1_reg_out_en <= '1';
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    phase1 <= '1', '0' after 10 ns;
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    wait;
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  end process;
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  -- end not in book
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end architecture rtl;
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-- end code from book
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