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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_15_dlxtstb.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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configuration dlx_test_behavior of dlx_test is
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  for bench
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    for cg : clock_gen
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      use entity work.clock_gen(behavior)
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        generic map ( Tpw => 8 ns, Tps => 2 ns );
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    end for;
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    for mem : memory
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      use entity work.memory(preloaded)
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        generic map ( mem_size => 65536,
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                      Tac_first => 95 ns, Tac_burst => 35 ns, Tpd_clk_out => 2 ns );
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    end for;
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    for proc : dlx
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      use entity work.dlx(behavior)
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        generic map ( Tpd_clk_out => 2 ns, debug => trace_each_step );
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    end for;
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  end for;
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end configuration dlx_test_behavior;
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