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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_15_dlxr.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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configuration dlx_rtl of dlx is
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  for rtl
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    for alu_s1_reg : latch
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      use entity work.latch(behavior)
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        generic map ( Tpd => 2 ns );
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    end for;
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    for alu_s2_reg : latch
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      use entity work.latch(behavior)
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        generic map ( Tpd => 2 ns );
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    end for;
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    for the_alu : alu
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      use entity work.alu(behavior)
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        generic map ( Tpd => 4 ns );
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    end for;
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    for the_reg_file : reg_file
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      use entity work.reg_file(behavior)
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        generic map ( Tac => 4 ns );
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    end for;
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    for c_reg : latch
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      use entity work.latch(behavior)
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        generic map ( Tpd => 2 ns );
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    end for;
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    for a_reg : reg_multiple_out
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      use entity work.reg_multiple_out(behavior)
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        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
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    end for;
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    for b_reg : reg_multiple_out
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      use entity work.reg_multiple_out(behavior)
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        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
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    end for;
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    for temp_reg : reg_multiple_out
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      use entity work.reg_multiple_out(behavior)
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        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
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    end for;
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    for iar_reg : reg_multiple_out
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      use entity work.reg_multiple_out(behavior)
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        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
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    end for;
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    for pc_reg :reg_multiple_plus_one_out_reset
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      use entity work.reg_multiple_plus_one_out_reset(behavior)
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        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
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    end for;
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    for mar_reg : reg_multiple_plus_one_out
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      use entity work.reg_multiple_plus_one_out(behavior)
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        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
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    end for;
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    for mem_addr_mux : mux2
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      use entity work.mux2(behavior)
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        generic map ( Tpd => 1 ns );
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    end for;
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    for mdr_reg : reg_multiple_out
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      use entity work.reg_multiple_out(behavior)
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        generic map ( num_outputs => num_outputs, Tpd => 2 ns );
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    end for;
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    for mdr_mux : mux2
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      use entity work.mux2(behavior)
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        generic map ( Tpd => 1 ns );
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    end for;
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    for instr_reg : latch
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      use entity work.latch(behavior)
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        generic map ( Tpd => 2 ns );
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    end for;
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    for ir_extender1 : ir_extender
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      use entity work.ir_extender(behavior)
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        generic map ( Tpd => 2 ns );
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    end for;
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    for ir_extender2 : ir_extender
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      use entity work.ir_extender(behavior)
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        generic map ( Tpd => 2 ns );
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    end for;
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    for the_controller : controller
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      use entity work.controller(behavior)
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        generic map ( Tpd_clk_ctrl => 2 ns, Tpd_clk_const => 4 ns,
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                      debug => debug );
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    end for;
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  end for;  -- rtl of dlx
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end configuration dlx_rtl;
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