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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_14_fg_14_09.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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package bus_monitor_pkg is
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  type stats_type is record
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                       ifetch_freq, write_freq, read_freq : real;
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                     end record stats_type;
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  component bus_monitor is
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                          generic ( verbose, dump_stats : boolean := false );
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                        port ( mem_req, ifetch, write : in bit;
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                               bus_stats : out stats_type );
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  end component bus_monitor;
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end package bus_monitor_pkg;
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use work.bus_monitor_pkg.all;
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entity bus_monitor is
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  generic ( verbose, dump_stats : boolean := false );
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  port ( mem_req, ifetch, write : in bit;
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         bus_stats : out stats_type );
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end entity bus_monitor;
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architecture general_purpose of bus_monitor is
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begin
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  access_monitor : process is
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                             variable access_count, ifetch_count,
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                           write_count, read_count : natural := 0;
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                           use std.textio;
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                           variable L : textio.line;
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  begin
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    wait until mem_req = '1';
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    if ifetch = '1' then
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      ifetch_count := ifetch_count + 1;
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      if verbose then
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        textio.write(L, string'("Ifetch"));
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        textio.writeline(textio.output, L);
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      end if;
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    elsif write = '1' then
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      write_count := write_count + 1;
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      if verbose then
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        textio.write(L, string'("Write"));
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        textio.writeline(textio.output, L);
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      end if;
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    else
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      read_count := read_count + 1;
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      if verbose then
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        textio.write(L, string'("Read"));
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        textio.writeline(textio.output, L);
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      end if;
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    end if;
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    access_count := access_count + 1;
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    bus_stats.ifetch_freq <= real(ifetch_count) / real(access_count);
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    bus_stats.write_freq <= real(write_count) / real(access_count);
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    bus_stats.read_freq <= real(read_count) / real(access_count);
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    if dump_stats and access_count mod 5 = 0 then
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      textio.write(L, string'("Ifetch frequency = "));
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      textio.write(L, real(ifetch_count) / real(access_count));
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      textio.writeline(textio.output, L);
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      textio.write(L, string'("Write frequency = "));
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      textio.write(L, real(write_count) / real(access_count));
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      textio.writeline(textio.output, L);
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      textio.write(L, string'("Read frequency = "));
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      textio.write(L, real(read_count) / real(access_count));
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      textio.writeline(textio.output, L);
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    end if;
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  end process access_monitor;
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end architecture general_purpose;
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-- code from book
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architecture block_level of computer_system is
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  -- . . .    -- type and component declarations for cpu and memory, etc.
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  signal clock : bit;    -- the system clock
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  signal mem_req : bit;  -- cpu access request to memory
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  signal ifetch : bit;   -- indicates access is to fetch an instruction
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  signal write : bit;    -- indicates access is a write
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  -- . . .                  -- other signal declarations
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begin
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  -- . . .    -- component instances for cpu and memory, etc.
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  instrumentation : if instrumented generate
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    use work.bus_monitor_pkg;
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    signal bus_stats : bus_monitor_pkg.stats_type;
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  begin
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    cpu_bus_monitor : component bus_monitor_pkg.bus_monitor
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      port map ( mem_req, ifetch, write, bus_stats );
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  end generate instrumentation;
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  -- not in book
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  stimulus : process is
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  begin
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    ifetch <= '1';  write <= '0';
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    mem_req <= '1', '0' after 10 ns;
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    wait for 20 ns;
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    mem_req <= '1', '0' after 10 ns;
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    ifetch <= '1';  write <= '0';
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    wait for 20 ns;
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    mem_req <= '1', '0' after 10 ns;
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    ifetch <= '1';  write <= '0';
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    wait for 20 ns;
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    mem_req <= '1', '0' after 10 ns;
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    ifetch <= '0';  write <= '1';
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    wait for 20 ns;
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    mem_req <= '1', '0' after 10 ns;
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    ifetch <= '1';  write <= '0';
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    wait for 20 ns;
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    mem_req <= '1', '0' after 10 ns;
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    ifetch <= '0';  write <= '0';
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    wait for 20 ns;
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    mem_req <= '1', '0' after 10 ns;
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    ifetch <= '1';  write <= '0';
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    wait for 20 ns;
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    mem_req <= '1', '0' after 10 ns;
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    ifetch <= '0';  write <= '0';
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    wait for 20 ns;
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    mem_req <= '1', '0' after 10 ns;
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    ifetch <= '1';  write <= '0';
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    wait for 20 ns;
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    mem_req <= '1', '0' after 10 ns;
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    ifetch <= '0';  write <= '0';
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    wait for 20 ns;
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    wait;
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  end process stimulus;
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  -- end not in book
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end architecture block_level;
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-- end code from book
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