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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_14_fg_14_06.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- code from book (in text)
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entity computer_system is
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  generic ( instrumented : boolean := false );
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  port ( -- . . . );
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    -- not in book
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    other_port : in bit := '0' );
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  -- end not in book
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end entity computer_system;
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-- end code from book
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-- code from book
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architecture block_level of computer_system is
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  -- . . .    -- type and component declarations for cpu and memory, etc
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  signal clock : bit;    -- the system clock
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  signal mem_req : bit;  -- cpu access request to memory
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  signal ifetch : bit;   -- indicates access is to fetch an instruction
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  signal write : bit;    -- indicates access is a write
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  -- . . .                  -- other signal declarations
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begin
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  -- . . .    -- component instances for cpu and memory, etc
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  instrumentation : if instrumented generate
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    signal ifetch_freq, write_freq, read_freq : real := 0.0;
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  begin
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    access_monitor : process is
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                               variable access_count, ifetch_count,
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                             write_count, read_count : natural := 0;
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    begin
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      wait until mem_req = '1';
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      if ifetch = '1' then
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        ifetch_count := ifetch_count + 1;
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      elsif write = '1' then
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        write_count := write_count + 1;
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      else
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        read_count := read_count + 1;
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      end if;
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      access_count := access_count + 1;
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      ifetch_freq <= real(ifetch_count) / real(access_count);
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      write_freq <= real(write_count) / real(access_count);
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      read_freq <= real(read_count) / real(access_count);
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    end process access_monitor;
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  end generate instrumentation;
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  -- not in book
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  stimulus : process is
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  begin
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    ifetch <= '1';  write <= '0';
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    mem_req <= '1', '0' after 10 ns;
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    wait for 20 ns;
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    mem_req <= '1', '0' after 10 ns;
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    ifetch <= '1';  write <= '0';
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    wait for 20 ns;
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    mem_req <= '1', '0' after 10 ns;
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    ifetch <= '1';  write <= '0';
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    wait for 20 ns;
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    mem_req <= '1', '0' after 10 ns;
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    ifetch <= '0';  write <= '1';
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    wait for 20 ns;
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    mem_req <= '1', '0' after 10 ns;
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    ifetch <= '1';  write <= '0';
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    wait for 20 ns;
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    mem_req <= '1', '0' after 10 ns;
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    ifetch <= '0';  write <= '0';
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    wait for 20 ns;
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    mem_req <= '1', '0' after 10 ns;
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    ifetch <= '1';  write <= '0';
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    wait for 20 ns;
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    mem_req <= '1', '0' after 10 ns;
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    ifetch <= '0';  write <= '0';
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    wait for 20 ns;
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    mem_req <= '1', '0' after 10 ns;
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    ifetch <= '1';  write <= '0';
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    wait for 20 ns;
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    mem_req <= '1', '0' after 10 ns;
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    ifetch <= '0';  write <= '0';
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    wait for 20 ns;
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    wait;
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  end process stimulus;
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  -- end not in book
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end architecture block_level;
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-- end code from book
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entity fg_14_06 is
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end entity fg_14_06;
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architecture test of fg_14_06 is
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  component computer_system is
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                              port ( other_port : in bit := '0' );
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  end component computer_system;
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begin
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  system_under_test : component computer_system
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    port map ( other_port => open );
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end architecture test;
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configuration fg_14_06_test of fg_14_06 is
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  for test
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    -- code from book (in text)
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    for system_under_test : computer_system
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      use entity work.computer_system(block_level)
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        generic map ( instrumented => true )
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        -- . . .
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        -- not in book
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        ;
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      -- end not in book
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    end for;
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    -- end code from book
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  end for;
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end configuration fg_14_06_test;
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