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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_14_ch_14_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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library ieee;  use ieee.std_logic_1164.all;
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               entity buf is
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                 port ( a : in std_logic;  y : out std_logic );
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               end buf;
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               architecture basic of buf is
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               begin
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                 y <= a;
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               end basic;
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               library ieee;  use ieee.std_logic_1164.all;
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               entity fanout_tree is
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                 generic ( height : natural );
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                 port ( input : in std_logic;
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                        output : out std_logic_vector (0 to 2**height - 1) );
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               end fanout_tree;
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--------------------------------------------------
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               architecture recursive of fanout_tree is
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                 component buf
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                   port ( a : in std_logic;  y : out std_logic );
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                 end component;
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                 component fanout_tree
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                   generic ( height : natural );
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                   port ( input : in std_logic;
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                          output : out std_logic_vector (0 to 2**height - 1) );
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                 end component;
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                 signal buffered_input_0, buffered_input_1 : std_logic;
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               begin
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                 degenerate_tree : if height = 0 generate
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                   output(0) <= input;
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                 end generate degenerate_tree;
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                 compound_tree : if height > 0 generate
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                   buf_0 : buf
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                     port map ( a => input, y => buffered_input_0 );
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                   -- code from book
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                   block_0 : block
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                     for subtree_0 : fanout_tree
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                       use entity work.fanout_tree(recursive);
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                   begin
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                     subtree_0 : fanout_tree
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                       generic map ( height => height - 1 )
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                       port map (  input => buffered_input_0,
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                                   output => output(0 to 2**(height - 1) - 1) );
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                   end block block_0;
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                   -- end code from book
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                   buf_1 : buf
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                     port map ( a => input, y => buffered_input_1 );
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                   block_1 : block
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                     for subtree_1 : fanout_tree
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                       use entity work.fanout_tree(recursive);
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                   begin
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                     subtree_1 : fanout_tree
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                       generic map ( height => height - 1 )
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                       port map ( input => buffered_input_1,
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                                  output => output(2**(height - 1) to 2**height - 1) );
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                   end block block_1;
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                 end generate compound_tree;
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               end recursive;
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               library ieee;  use ieee.std_logic_1164.all;
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               entity ch_14_01 is
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               end ch_14_01;
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               architecture test of ch_14_01 is
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                 component fanout_tree
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                   generic ( height : natural );
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                   port ( input : in std_logic;
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                          output : out std_logic_vector (0 to 2**height - 1) );
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                 end component;
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                 for clock_buffer_tree : fanout_tree
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                   use entity work.fanout_tree(recursive);
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                 signal unbuffered_clock : std_logic;
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                 signal buffered_clock_array : std_logic_vector(0 to 7);
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               begin
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                 clock_buffer_tree : fanout_tree
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                   generic map ( height => 3 )
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                   port map ( input => unbuffered_clock,
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                              output => buffered_clock_array );
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                 clock_gen : process
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                 begin
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                   unbuffered_clock <= '1' after 5 ns, '0' after 10 ns;
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                   wait for 10 ns;
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                 end process clock_gen;
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               end test;
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