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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_13_fg_13_19.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- code from book (in text)
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entity nand3 is
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  port ( a, b, c : in bit;  y : out bit );
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end entity nand3;
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-- end code from book
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architecture behavioral of nand3 is
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begin
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  y <= not (a and b and c);
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end architecture behavioral;
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entity logic_block is
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end entity logic_block;
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-- code from book
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library gate_lib;
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architecture ideal of logic_block is
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  component nand2 is
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                    port ( in1, in2 : in bit;  result : out bit );
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  end component nand2;
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  for all : nand2
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    use entity gate_lib.nand3(behavioral)
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    port map ( a => in1, b => in2, c => '1', y => result );
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  -- . . .    -- other declarations
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  -- not in book
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  signal s1, s2, s3 : bit := '0';
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begin
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  gate1 : component nand2
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    port map ( in1 => s1, in2 => s2, result => s3 );
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  -- . . .    -- other concurrent statements
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  -- not in book
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  s1 <= '1' after 20 ns;
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  s2 <= '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
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  -- end not in book
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end architecture ideal;
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-- end code from book
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