Project

General

Profile

Download (2.11 KB) Statistics
| Branch: | Tag: | Revision:
1

    
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3

    
4
-- This file is part of VESTs (Vhdl tESTs).
5

    
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10

    
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15

    
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19

    
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_13_fg_13_05.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
23
-- $Revision: 1.3 $
24
--
25
-- ---------------------------------------------------------------------
26

    
27
-- code from book
28

    
29
library star_lib;
30
--use star_lib.edge_triggered_Dff;
31
use star_lib.all;
32

    
33
configuration reg4_gate_level of reg4 is
34

    
35
  for struct  -- architecture of reg4
36

    
37
    for bit0 : flipflop
38
      use entity star_lib.edge_triggered_Dff(hi_fanout);
39
    end for;
40

    
41
    for others : flipflop
42
      use entity star_lib.edge_triggered_Dff(basic);
43
    end for;
44

    
45
  end for;  -- end of architecture struct
46

    
47
end configuration reg4_gate_level;
48

    
49
-- end code from book
50

    
51

    
52
entity fg_13_05 is
53
end entity fg_13_05;
54

    
55

    
56
architecture test of fg_13_05 is
57

    
58
  component reg4 is
59
                   port ( clk, clr : in bit;  d : in bit_vector(0 to 3);
60
                   q : out bit_vector(0 to 3) );
61
  end component reg4;
62

    
63
  signal clk, clr : bit;
64
  signal d, q : bit_vector(0 to 3);
65

    
66
begin
67

    
68
  flag_reg : component reg4
69
    port map ( clk => clk, clr => clr, d => d, q => q );
70

    
71
end architecture test;
72

    
73

    
74
configuration fg_13_05_test of fg_13_05 is
75

    
76
  for test
77

    
78
    -- code from book (in text)
79

    
80
    for flag_reg : reg4
81
      use configuration work.reg4_gate_level;
82
    end for;
83

    
84
    -- end code from book
85

    
86
  end for;
87

    
88
end configuration fg_13_05_test;
(63-63/171)