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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_12_fg_12_02.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- code from book
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entity D_flipflop is
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  generic ( Tpd_clk_q, Tsu_d_clk, Th_d_clk : delay_length );
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  port ( clk, d : in bit;  q : out bit );
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end entity D_flipflop;
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--------------------------------------------------
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architecture basic of D_flipflop is
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begin
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  behavior : q <= d after Tpd_clk_q when clk = '1' and clk'event;
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  check_setup : process is
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  begin
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    wait until clk = '1';
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    assert d'last_event >= Tsu_d_clk
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      report "setup violation";
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  end process check_setup;
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  check_hold : process is
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  begin
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    wait until clk'delayed(Th_d_clk) = '1';
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    assert d'delayed'last_event >= Th_d_clk
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      report "hold violation";
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  end process check_hold;
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end architecture basic;
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-- end code from book
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entity fg_12_02 is
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end entity fg_12_02;
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architecture test of fg_12_02 is
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  signal system_clock, request, request_pending : bit := '0';
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begin
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  -- code from book (in text)
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  request_flipflop : entity work.D_flipflop(basic)
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    generic map ( Tpd_clk_q => 4 ns,
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                  Tsu_d_clk => 3 ns, Th_d_clk => 1 ns )
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    port map ( clk => system_clock,
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               d => request, q => request_pending );
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  -- end code from book
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  clock_gen : system_clock <= '1' after 10 ns,
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                              '0' after 20 ns when system_clock = '0';
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  stimulus :  request <= '1' after  25 ns, '0' after  35 ns,
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                         '1' after  67 ns, '0' after  71 ns,
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                         '1' after 108 ns, '0' after 110.5 ns;
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end architecture test;
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