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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_12_ch_12_01.vhd,v 1.2 2001-10-24 23:31:00 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- code from book
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entity and2 is
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  generic ( Tpd : time );
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  port ( a, b : in bit;  y : out bit );
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end entity and2;
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architecture simple of and2 is
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begin
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  and2_function :
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    y <= a and b after Tpd;
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end architecture simple;
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-- end code from book
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entity ch_12_01 is
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end entity ch_12_01;
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library stimulus;
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use stimulus.stimulus_generators.all;
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architecture test of ch_12_01 is
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  signal a1, b1, sig1, sig2, sig_out : bit;
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  signal test_vector : bit_vector(1 to 3);
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begin
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  -- code from book
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  gate1 : entity work.and2(simple)
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    generic map ( Tpd => 2 ns )
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    port map ( a => sig1,  b => sig2,  y => sig_out );
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  gate2 : entity work.and2(simple)
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    generic map ( Tpd => 3 ns )
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    port map ( a => a1,  b => b1,  y => sig1 );
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  -- end code from book
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  stimulus : all_possible_values ( bv => test_vector,
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				   delay_between_values => 10 ns );
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  (sig2, a1, b1) <= test_vector;
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end architecture test;
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