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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_11_ch_11_01.vhd,v 1.2 2001-10-26 16:29:35 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_11_01 is
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end entity ch_11_01;
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----------------------------------------------------------------
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architecture test of ch_11_01 is
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  type MVL4_ulogic is ('X', '0', '1', 'Z');  -- unresolved logic type
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  -- code from book:
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  type small_int is range 1 to 4;
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  type small_array is array (small_int range <>) of -- . . . ;
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    -- not in book
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    MVL4_ulogic;
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  -- end not in book
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  -- end of code from book
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  type table is array (MVL4_ulogic, MVL4_ulogic) of MVL4_ulogic;
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  constant resolution_table : table :=
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    --  'X'  '0'  '1'  'Z'
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    --  ------------------
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    ( ( 'X', 'X', 'X', 'X' ),    -- 'X'
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      ( 'X', '0', 'X', '0' ),    -- '0'
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      ( 'X', 'X', '1', '1' ),    -- '1'
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      ( 'X', '0', '1', 'Z' ) );  -- 'Z'
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  function resolve_MVL4 ( contribution : small_array ) return MVL4_ulogic is
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    variable result : MVL4_ulogic := 'Z';
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  begin
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    for index in contribution'range loop
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      result := resolution_table(result, contribution(index));
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    end loop;
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    return result;
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  end function resolve_MVL4;
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  subtype MVL4_logic is resolve_MVL4 MVL4_ulogic;
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  signal s : MVL4_logic;
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begin
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  driver_1 : s <= 'Z';
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  driver_2 : s <= 'Z';
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  driver_3 : s <= 'Z';
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  driver_4 : s <= 'Z';
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  driver_5 : s <= 'Z';
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end architecture test;
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