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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_08_fg_08_10.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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entity fg_08_10 is
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end entity fg_08_10;
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architecture test of fg_08_10 is
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  -- code from book
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  function "<" ( a, b : bit_vector ) return boolean is
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    variable tmp1 : bit_vector(a'range) := a;
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    variable tmp2 : bit_vector(b'range) := b;
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  begin
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    tmp1(tmp1'left) := not tmp1(tmp1'left);
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    tmp2(tmp2'left) := not tmp2(tmp2'left);
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    return std.standard."<" ( tmp1, tmp2 );
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  end function "<";
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  -- end code from book
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  signal a, b : bit_vector(7 downto 0);
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  signal result : boolean;
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begin
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  dut : result <= a < b;
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  stimulus : process is
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  begin
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    wait for 10 ns;
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    a <= X"02";  b <= X"04";  wait for 10 ns;
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    a <= X"02";  b <= X"02";  wait for 10 ns;
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    a <= X"02";  b <= X"01";  wait for 10 ns;
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    a <= X"02";  b <= X"FE";  wait for 10 ns;
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    a <= X"FE";  b <= X"02";  wait for 10 ns;
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    a <= X"FE";  b <= X"FE";  wait for 10 ns;
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    a <= X"FE";  b <= X"FC";  wait for 10 ns;
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    wait;
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  end process stimulus;
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end architecture test;
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