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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_08_fg_08_07.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- not in book
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entity cpu is
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end entity cpu;
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-- end not in book
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architecture behavioral of cpu is
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begin
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  interpreter : process is
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                          variable instr_reg : work.cpu_types.word;
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                        variable instr_opcode : work.cpu_types.opcode;
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  begin
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    -- . . .    -- initialize
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    loop
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      -- . . .    -- fetch instruction
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      instr_opcode := work.cpu_types.extract_opcode ( instr_reg );
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      case instr_opcode is
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        when work.cpu_types.op_nop => null;
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        when work.cpu_types.op_breq => -- . . .
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          -- . . .
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          -- not in book
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        when others => null;
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                       -- end not in book
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      end case;
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    end loop;
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  end process interpreter;
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end architecture behavioral;
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