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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_08_fg_08_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- not in book
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library ieee;  use ieee.std_logic_1164.all;
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               entity phase_locked_clock_gen is
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                 port ( reference : in std_ulogic;
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                        phi1, phi2 : out std_ulogic );
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               end entity phase_locked_clock_gen;
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               architecture std_cell of phase_locked_clock_gen is
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                 --use work.clock_pkg.Tpw;
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                 use work.clock_pkg.all;
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               begin
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                 phi1_gen : phi1 <= '1', '0' after Tpw when rising_edge(reference);
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                 phi2_gen : phi2 <= '1', '0' after Tpw when falling_edge(reference);
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               end architecture std_cell;
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-- end not in book
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               library ieee;  use ieee.std_logic_1164.all;
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               entity io_controller is
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                 port ( ref_clock : in std_ulogic;  -- . . . );
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                        -- not in book
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                        other_port : in std_ulogic );
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                 -- end not in book
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               end entity io_controller;
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--------------------------------------------------
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               architecture top_level of io_controller is
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                 -- . . .
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                 -- not in book
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                 signal rd, wr, sel, width, burst : std_ulogic;
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                 signal addr : std_ulogic_vector(1 downto 0);
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                 signal ready : std_ulogic;
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                 signal control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
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                   other_signal : std_ulogic;
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                 -- end not in book
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               begin
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                 internal_clock_gen : entity work.phase_locked_clock_gen(std_cell)
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                   port map ( reference => ref_clock,
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                              phi1 => work.clock_pkg.clock_phase1,
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                              phi2 => work.clock_pkg.clock_phase2 );
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                 the_bus_sequencer : entity work.bus_sequencer(fsm)
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                   port map ( rd, wr, sel, width, burst, addr(1 downto 0), ready,
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                              control_reg_wr, status_reg_rd, data_fifo_wr, data_fifo_rd,
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                              -- . . . );
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                              other_signal );
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                 -- not in book
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                 -- . . .
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               end architecture top_level;
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