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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_08_ch_08_05.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- code from book:
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library std, work;  use std.standard.all;
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-- end of code from book
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                    entity ch_08_05 is
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                    end entity ch_08_05;
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----------------------------------------------------------------
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                    architecture test of ch_08_05 is
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                    begin
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                      process_08_4_a : process is
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                                                 constant a : integer := 10;
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                                               constant b : integer := 20;
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                                               variable result : boolean;
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                      begin
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                        -- code from book:
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                        result := std.standard."<" ( a, b );
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                        -- end of code from book
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                        wait;
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                      end process process_08_4_a;
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                    end architecture test;
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