Project

General

Profile

Download (2.89 KB) Statistics
| Branch: | Tag: | Revision:
1

    
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3

    
4
-- This file is part of VESTs (Vhdl tESTs).
5

    
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10

    
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15

    
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19

    
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_07_fg_07_05.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
23
-- $Revision: 1.2 $
24
--
25
-- ---------------------------------------------------------------------
26

    
27
entity fg_07_05 is
28
end entity fg_07_05;
29

    
30

    
31
architecture interpreter of fg_07_05 is
32

    
33
  subtype word is bit_vector(31 downto 0);
34

    
35
  signal address_bus, data_bus_in : word := X"0000_0000";
36
  signal mem_read, mem_request, mem_ready, reset : bit := '0';
37

    
38
begin
39

    
40
  -- code from book
41

    
42
  instruction_interpreter : process is
43

    
44
                                      -- . . .
45

    
46
                                      -- not in book
47
                                      variable mem_address_reg, mem_data_reg : word;
48
                                    -- end not in book
49

    
50
                                    procedure read_memory is
51
                                    begin
52
                                      address_bus <= mem_address_reg;
53
                                      mem_read <= '1';
54
                                      mem_request <= '1';
55
                                      wait until mem_ready = '1' or reset = '1';
56
                                      if reset = '1' then
57
                                        return;
58
                                      end if;
59
                                      mem_data_reg := data_bus_in;
60
                                      mem_request <= '0';
61
                                      wait until mem_ready = '0';
62
                                    end procedure read_memory;
63

    
64
  begin
65
    -- . . .    -- initialization
66
    -- not in book
67
    if reset = '1' then
68
      wait until reset = '0';
69
    end if;
70
    -- end not in book
71
    loop
72
      -- . . .
73
      read_memory;
74
      exit when reset = '1';
75
      -- . . .
76
    end loop;
77
  end process instruction_interpreter;
78

    
79
  -- end code from book
80

    
81

    
82
  memory : process is
83
  begin
84
    wait until mem_request = '1';
85
    data_bus_in <= X"1111_1111";
86
    mem_ready <= '1' after 10 ns;
87
    wait until mem_request = '0';
88
    mem_ready <= '0' after 10 ns;
89
  end process memory;
90

    
91
  reset <= '1' after 85 ns;
92

    
93
end architecture interpreter;
(39-39/171)