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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_07_ch_07_02.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_07_02 is
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end entity ch_07_02;
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----------------------------------------------------------------
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architecture test of ch_07_02 is
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  constant val1 : integer := 1;
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  procedure p ( signal s1, s2 : in bit;  val1 : in integer ) is
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  begin
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    null;
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  end procedure p;
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begin
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  block_07_3_a : block is
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                         signal s1, s2 : bit;
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  begin
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    -- code from book:
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    call_proc : p ( s1, s2, val1 );
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    -- end of code from book
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  end block block_07_3_a;
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  ----------------
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  block_07_3_b : block is
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                         signal s1, s2 : bit;
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  begin
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    -- code from book:
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    call_proc : process is
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    begin
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      p ( s1, s2, val1 );
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      wait on s1, s2;
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    end process call_proc;
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    -- end of code from book
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  end block block_07_3_b;
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end architecture test;
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