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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_tb_05_09.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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entity tb_05_09 is
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end entity tb_05_09;
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architecture test of tb_05_09 is
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  signal clk, clr, d0, d1, d2, d3 : bit := '0';
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  signal q0, q1, q2, q3 : bit;
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begin
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  dut : entity work.reg4(struct)
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    port map ( clk => clk, clr => clr,
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	       d0 => d0, d1 => d1, d2 => d2, d3 => d3,
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	       q0 => q0, q1 => q1, q2 => q2, q3 => q3 );
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  stimulus : process is
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  begin
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    (d3, d2, d1, d0) <= bit_vector'(b"1010");	wait for 10 ns;
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    clk <= '1';					wait for 10 ns;
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    (d3, d2, d1, d0) <= bit_vector'(b"0101");	wait for 10 ns;
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    clk <= '0';					wait for 10 ns;
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    (d3, d2, d1, d0) <= bit_vector'(b"1111");	wait for 10 ns;
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    clr <= '1';					wait for 10 ns;
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    clk <= '1';					wait for 10 ns;
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    clr <= '0';					wait for 10 ns;
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    clk <= '0';					wait for 10 ns;
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    wait;
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  end process stimulus;
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end architecture test;
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