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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_tb_05_04.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity tb_05_04 is
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end entity tb_05_04;
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architecture test of tb_05_04 is
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  signal a, b, sel, z : bit;
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begin
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  dut : entity work.mux2(behavioral)
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    port map ( a => a, b => b, sel => sel, z => z );
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  stimulus : process is
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                       subtype stim_vector_type is bit_vector(0 to 3);
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                     type stim_vector_array is array ( natural range <> ) of stim_vector_type;
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                     constant stim_vector : stim_vector_array
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                       := ( "0000",
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                            "0100",
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                            "1001",
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                            "1101",
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                            "0010",
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                            "0111",
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                            "1010",
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                            "1111" );
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  begin
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    for i in stim_vector'range loop
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      (a, b, sel) <= stim_vector(i)(0 to 2);
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      wait for 10 ns;
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      assert z = stim_vector(i)(3);
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    end loop;
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    wait;
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  end process stimulus;
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end architecture test;
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