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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_fg_05_17.vhd,v 1.5 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.5 $
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--
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-- ---------------------------------------------------------------------
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entity fg_05_17 is
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end entity fg_05_17;
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library stimulus;
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architecture test of fg_05_17 is
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  use stimulus.stimulus_generators.all;
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  signal sel0, sel1, d0, d1, d2, d3 : bit := '0';
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  signal functional_z, equivalent_z : bit;
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begin
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  functional_mux : block is
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                           port ( z : out bit );
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                         port map ( z => functional_z );
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  begin
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    -- code from book
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    zmux : z <= d0 when sel1 = '0' and sel0 = '0' else
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                d1 when sel1 = '0' and sel0 = '1' else
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                d2 when sel1 = '1' and sel0 = '0' else
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                d3 when sel1 = '1' and sel0 = '1';
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    -- end code from book
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  end block functional_mux;
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  equivalent_mux : block is
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                           port ( z : out bit );
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                         port map ( z => equivalent_z );
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  begin
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    -- code from book
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    zmux : process is
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    begin
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      if sel1 = '0' and sel0 = '0' then
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        z <= d0;
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      elsif sel1 = '0' and sel0 = '1' then
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        z <= d1;
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      elsif sel1 = '1' and sel0 = '0' then
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        z <= d2;
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      elsif sel1 = '1' and sel0 = '1' then
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        z <= d3;
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      end if;
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      wait on d0, d1, d2, d3, sel0, sel1;
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    end process zmux;
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    -- end code from book
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  end block equivalent_mux;
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  stimulus_proc :
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    all_possible_values( bv(0) => sel0, bv(1) => sel1,
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			 bv(2) => d0, bv(3) => d1,
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			 bv(4) => d2, bv(5) => d3,
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			 delay_between_values => 10 ns );
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  verifier :
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    assert functional_z = equivalent_z
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      report "Functional and equivalent models give different results";
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end architecture test;
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