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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_ch_05_23.vhd,v 1.2 2001-10-24 23:30:59 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- code from book:
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entity and_or_inv is
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  port ( a1, a2, b1, b2 : in bit := '1';
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         y : out bit );
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end entity and_or_inv;
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-- end of code from book
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architecture functional of and_or_inv is
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begin
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  func : y <= not ((a1 and a2) or (b1 and b2));
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end architecture functional;
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entity ch_05_23 is
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end entity ch_05_23;
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library stimulus;
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architecture test of ch_05_23 is
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  signal A, B, C, F : bit;
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  signal test_input : bit_vector(2 downto 0);
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  use stimulus.stimulus_generators.all;
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begin
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  -- code from book:
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  f_cell : entity work.and_or_inv
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    port map (a1 => A, a2 => B, b1 => C, b2 => open, y => F);
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  -- end of code from book
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  stimulus_proc : all_possible_values( bv => test_input,
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				  delay_between_values => 10 ns );
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  (A, B, C) <= test_input;
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  verifier :
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    postponed assert F = not ((A and B) or C)
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      report "function model produced unexpected result";
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end architecture test;
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