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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_ch_05_18.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- code from book:
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entity DRAM_controller is
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  port ( rd, wr, mem : in bit;
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         ras, cas, we, ready : out bit  );
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end entity DRAM_controller;
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-- end of code from book
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----------------------------------------------------------------
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architecture fpld of DRAM_controller is
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begin
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end architecture fpld;
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----------------------------------------------------------------
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entity ch_05_18 is
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end entity ch_05_18;
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----------------------------------------------------------------
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architecture test of ch_05_18 is
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begin
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  block_05_4_a : block is
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                         signal cpu_rd, cpu_wr, cpu_mem,
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                       mem_ras, mem_cas, mem_we, cpu_rdy : bit;
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  begin
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    -- code from book:
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    main_mem_controller : entity work.DRAM_controller(fpld)
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      port map ( cpu_rd, cpu_wr, cpu_mem,
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                 mem_ras, mem_cas, mem_we, cpu_rdy );
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    -- end of code from book
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  end block block_05_4_a;
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  ----------------
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  block_05_4_b : block is
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                         signal cpu_rd, cpu_wr, cpu_mem,
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                       mem_ras, mem_cas, mem_we, cpu_rdy : bit;
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  begin
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    -- code from book:
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    main_mem_controller : entity work.DRAM_controller(fpld)
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      port map ( rd => cpu_rd, wr => cpu_wr,
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                 mem => cpu_mem, ready => cpu_rdy,
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                 ras => mem_ras, cas => mem_cas, we => mem_we );
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    -- end of code from book
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  end block block_05_4_b;
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end architecture test;
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