Project

General

Profile

Download (2.2 KB) Statistics
| Branch: | Tag: | Revision:
1

    
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3

    
4
-- This file is part of VESTs (Vhdl tESTs).
5

    
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10

    
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15

    
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19

    
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_05_ch_05_14.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
23
-- $Revision: 1.2 $
24
--
25
-- ---------------------------------------------------------------------
26

    
27
entity ch_05_14 is
28

    
29
end entity ch_05_14;
30

    
31

    
32
----------------------------------------------------------------
33

    
34

    
35
architecture test of ch_05_14 is
36

    
37
  signal PC, functional_next_PC, equivalent_next_PC : integer := 0;
38

    
39
begin
40

    
41

    
42
  block_05_3_p : block is
43
                         port ( next_PC : out integer );
44
                       port map ( next_PC => functional_next_PC );
45
  begin
46

    
47
    -- code from book:
48

    
49
    PC_incr : next_PC <= PC + 4 after 5 ns;
50

    
51
    -- end of code from book
52

    
53
  end block block_05_3_p;
54

    
55

    
56
  ----------------
57

    
58

    
59
  block_05_3_q : block is
60
                         port ( next_PC : out integer );
61
                       port map ( next_PC => equivalent_next_PC );
62
  begin
63

    
64
    -- code from book:
65

    
66
    PC_incr : process is
67
    begin
68
      next_PC <= PC + 4 after 5 ns;
69
      wait on PC;
70
    end process PC_incr;
71

    
72
    -- end of code from book
73

    
74
  end block block_05_3_q;
75

    
76

    
77
  ----------------
78

    
79

    
80
  stimulus : process is
81
  begin
82
    for i in 1 to 10 loop
83
      PC <= i after 20 ns;
84
      wait for 20 ns;
85
    end loop;
86
    wait;
87
  end process stimulus;
88

    
89
  verifier :
90
    assert functional_next_PC = equivalent_next_PC
91
      report "Functional and equivalent models give different results";
92

    
93

    
94
end architecture test;
(23-23/171)