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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_05_ch_05_08.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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entity ch_05_08 is
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end entity ch_05_08;
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library stimulus;
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architecture test of ch_05_08 is
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  constant T_pd : delay_length := 5 ns;
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  signal a, b : bit := '0';
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  signal test_inputs : bit_vector(1 to 2);
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  use stimulus.stimulus_generators.all;
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begin
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  block_05_3_f : block is
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                         signal sum, carry : bit;
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  begin
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    -- code from book:
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    half_add : process is
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    begin
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      sum <= a xor b after T_pd;
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      carry <= a and b after T_pd;
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      wait on a, b;
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    end process half_add;
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    -- end of code from book
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  end block block_05_3_f;
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  block_05_3_g : block is
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                         signal sum, carry : bit;
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  begin
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    -- code from book:
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    half_add : process (a, b) is
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    begin
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      sum <= a xor b after T_pd;
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      carry <= a and b after T_pd;
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    end process half_add;
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    -- end of code from book
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  end block block_05_3_g;
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  stimulus_05_3_f_g :
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    all_possible_values(test_inputs, 20 ns);
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  (a, b) <= test_inputs;
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end architecture test;
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