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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_04_ch_04_10.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity ch_04_10 is
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end entity ch_04_10;
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----------------------------------------------------------------
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architecture test of ch_04_10 is
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  -- code from book:
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  type time_stamp is record
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                       seconds : integer range 0 to 59;
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                       minutes : integer range 0 to 59;
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                       hours : integer range 0 to 23;
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                     end record time_stamp;
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  -- end of code from book
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begin
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  process_04_4_a : process is
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                             -- code from book:
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                             variable sample_time, current_time : time_stamp;
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                           --
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                           constant midday : time_stamp := (0, 0, 12);
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                           -- end of code from book
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                           constant clock : integer := 79;
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                           variable sample_hour : integer;
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  begin
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    current_time := (30, 15, 2);
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    -- code from book:
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    sample_time := current_time;
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    sample_hour := sample_time.hours;
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    current_time.seconds := clock mod 60;
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    -- end of code from book
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    wait;
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  end process process_04_4_a;
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  process_04_4_b : process is
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                             type opcodes is (add, sub, addu, subu, jmp, breq, brne, ld, st, nop);
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                           type reg_number is range 0 to 31;
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                           type instruction is record
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                                                 opcode : opcodes;
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                                                 source_reg1, source_reg2, dest_reg : reg_number;
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                                                 displacement : integer;
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                                               end record instruction;
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                           -- code from book:
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                           constant midday : time_stamp := (hours => 12, minutes => 0, seconds => 0);
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                           --
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                           constant nop_instr : instruction :=
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                             ( opcode => addu,
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                               source_reg1 | source_reg2 | dest_reg => 0,
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                               displacement => 0 );
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                           variable latest_event : time_stamp := (others => 0); -- initially midnight
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                           -- end of code from book
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  begin
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    wait;
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  end process process_04_4_b;
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end architecture test;
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