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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ap_a_fg_a_11.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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library ieee;  use ieee.std_logic_1164.all;
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               entity RAM16x1 is
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                 port ( \a<0>\, \a<1>\, \a<2>\, \a<3>\ : in std_ulogic;
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                        \d\, \we\ : in std_ulogic;
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                        \o\ : out std_ulogic );
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               end entity RAM16x1;
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               architecture a of RAM16x1 is
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               begin
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               end architecture a;
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               entity fg_a_11 is
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               end entity fg_a_11;
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               library ieee;  use ieee.std_logic_1164.all;
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               architecture test of fg_a_11 is
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                 -- code from book
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                 component RAM16x1 is
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                                     port ( \a<0>\, \a<1>\, \a<2>\, \a<3>\ : in std_ulogic;
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                                            \d\, \we\ : in std_ulogic;
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                                            \o\ : out std_ulogic );
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                 end component RAM16x1;
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                 -- . . .
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                 -- end code from book
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                 signal address : std_ulogic_vector(3 downto 0);
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                 signal raminp, ramout : std_ulogic_vector(15 downto 0);
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                 signal write_enable : std_ulogic;
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               begin
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                 -- code from book
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                 g1 : for i in 0 to 15 generate
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                   rama : component RAM16x1
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                     port map ( \a<0>\ => address(0),
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                                \a<1>\ => address(1),
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                                \a<2>\ => address(2),
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                                \a<3>\ => address(3),
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                                \d\ => raminp ( i ),
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                                \we\ => write_enable,
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                                \o\ => ramout ( i ) );
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                 end generate g1;
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                 -- end code from book
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               end architecture test;
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