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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ap_a_fg_a_03.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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-- code from book
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library ieee;  use ieee.std_logic_1164.all;
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               entity add_and_sub is
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                 port ( a, b, c : in natural;
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                        y : out natural;
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                        ovf : out std_ulogic );
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               end entity add_and_sub;
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--------------------------------------------------
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               library ieee;  use ieee.numeric_std.all;
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               architecture rtl of add_and_sub is
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                 signal stage2, stage3 : unsigned ( 8 downto 0 );
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               begin
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                 stage2 <= To_unsigned(a, 9) + to_unsigned(b, 9);  -- "+" from numeric_std
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                 stage3 <= stage2 - c;              -- "-" from numeric_std
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                 y <= To_integer(stage3) ;
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                 ovf <= stage3(8);
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               end rtl;
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-- end code from book
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               entity fg_a_03 is
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               end entity fg_a_03;
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               library ieee;
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               use ieee.std_logic_1164.all, ieee.numeric_std.all;
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               architecture test of fg_a_03 is
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                 signal a, b, c, y : natural := 0;
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                 signal ovf : std_ulogic;
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               begin
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                 dut : entity work.add_and_sub
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                   port map ( a, b, c, y, ovf );
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                 stimulus : process is
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                 begin
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                   wait for 10 ns;
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                   a <= 2;  b <= 5;  c <= 3;  wait for 10 ns;
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                   a <= 192;  b <= 192;  wait for 10 ns;
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                   a <= 10;  b <= 11;  c <= 22;  wait for 10 ns;
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                   wait;
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                 end process stimulus;
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               end architecture test;
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