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 Copyright (C) 1996 Morgan Kaufmann Publishers, Inc

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 This file is part of VESTs (Vhdl tESTs).

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 VESTs is free software; you can redistribute it and/or modify it

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 under the terms of the GNU General Public License as published by the

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 Free Software Foundation; either version 2 of the License, or (at

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 your option) any later version.

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 VESTs is distributed in the hope that it will be useful, but WITHOUT

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 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or

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 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License

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 for more details.

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 You should have received a copy of the GNU General Public License

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 along with VESTs; if not, write to the Free Software Foundation,

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 Inc., 59 Temple Place, Suite 330, Boston, MA 021111307 USA

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20

 

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 $Id: ap_a_ap_a_02.vhd,v 1.2 20011026 16:29:33 paw Exp $

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 $Revision: 1.2 $

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entity ap_a_02 is

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end entity ap_a_02;

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library ieee; use ieee.std_logic_1164.all;

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architecture test of ap_a_02 is

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 code from book

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 end code from book

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begin

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b1 : block is

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signal sulv : std_ulogic_vector(7 downto 0);

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signal slv : std_logic_vector(7 downto 0);

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begin

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 code from book

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sulv <= To_stdulogicvector ( slv );

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 end code from book

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slv <= "10101010";

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end block b1;

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b2 : block is

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signal sulv : std_ulogic_vector(7 downto 0);

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signal slv : std_logic_vector(7 downto 0);

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begin

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 code from book

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slv <= To_stdlogicvector ( sulv );

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 end code from book

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sulv <= "00001111";

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end block b2;

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b3 : block is

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signal a, ena, y : std_logic;

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begin

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 code from book

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y <= a when ena = '1' else

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'Z';

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 end code from book

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ena <= '0', '1' after 20 ns, '0' after 40 ns;

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a <= '0', '1' after 10 ns, '0' after 30 ns, '1' after 50 ns;

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end block b3;

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b4 : block is

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signal a, ena, y : std_logic;

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begin

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 code from book

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y <= a when ena = '1' else

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'H';

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 end code from book

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ena <= '0', '1' after 20 ns, '0' after 40 ns;

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a <= '0', '1' after 10 ns, '0' after 30 ns, '1' after 50 ns;

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end block b4;

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b5 : block is

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signal a, b, x, s, y : std_logic;

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begin

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 code from book

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y <= a when x = '1' else

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b when s = '1' else

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'';

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 end code from book

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x <= '0', '1' after 20 ns, '0' after 40 ns;

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s <= '0', '1' after 60 ns, '0' after 80 ns;

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a <= '0', '1' after 10 ns, '0' after 30 ns,

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'1' after 50 ns, '0' after 70 ns,

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'1' after 90 ns;

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b <= '0', '1' after 15 ns, '0' after 35 ns,

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'1' after 55 ns, '0' after 75 ns,

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'1' after 95 ns;

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end block b5;

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end architecture test;

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