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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_21_fg_21_06.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity multiprocessor is
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end entity multiprocessor;
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-- code from book
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architecture instrumented of multiprocessor is
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  -- not in book
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  constant num_processors : positive := 2;
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  -- end not in book
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  shared variable bus_ifetch_count,
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    bus_read_count,
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    bus_write_count : natural := 0;
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  signal bus_request, bus_grant : bit_vector(0 to num_processors - 1);
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  -- . . .    -- other signal declarations
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begin
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  processor_array :
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  for processor_id in 0 to num_processors - 1 generate
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    processor : process is
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                          -- . . .
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    begin
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      -- . . .    -- initialize
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      loop
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        bus_request(processor_id) <= '1';
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        wait until bus_grant(processor_id) = '1';
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        bus_ifetch_count := bus_ifetch_count + 1;
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        -- . . .    -- fetch instruction
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        bus_request(processor_id) <= '0';
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        -- . . .    -- decode and execute instruction
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        -- not in book
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        wait until bus_grant(processor_id) = '0';
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        -- end not in book
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      end loop;
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    end process processor;
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  end generate processor_array;
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  arbiter : process is
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  begin
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    -- . . .
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    -- not in book
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    loop
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      for i in bus_request'range loop
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        if bus_request(i) = '1' then
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          bus_grant(i) <= '1' after 5 ns;
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          wait until bus_request(i) = '0';
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          bus_grant(i) <= '0' after 5 ns;
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        end if;
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      end loop;
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      wait for 5 ns;
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    end loop;
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    -- end not in book
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  end process arbiter;
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  -- . . .    -- other processes for memory, etc
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end architecture instrumented;
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-- end code from book
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