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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_20_fg_20_16.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity fg_20_16 is
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end entity fg_20_16;
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architecture test of fg_20_16 is
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  signal clk : bit;
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  attribute synthesis_hint : string;
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begin
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  -- code from book
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  controller : process is
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                         attribute synthesis_hint of control_loop : label is
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                       "implementation:FSM(clk)";
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                       -- . . .
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  begin
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    -- . . .    -- initialization
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    control_loop : loop
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      wait until clk = '1';
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      -- . . .
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    end loop;
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  end process controller;
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  -- end code fom book
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end architecture test;
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