Project

General

Profile

Download (2.25 KB) Statistics
| Branch: | Tag: | Revision:
1

    
2
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
3

    
4
-- This file is part of VESTs (Vhdl tESTs).
5

    
6
-- VESTs is free software; you can redistribute it and/or modify it
7
-- under the terms of the GNU General Public License as published by the
8
-- Free Software Foundation; either version 2 of the License, or (at
9
-- your option) any later version. 
10

    
11
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
12
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13
-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
14
-- for more details. 
15

    
16
-- You should have received a copy of the GNU General Public License
17
-- along with VESTs; if not, write to the Free Software Foundation,
18
-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
19

    
20
-- ---------------------------------------------------------------------
21
--
22
-- $Id: ch_16_fg_16_01.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
23
-- $Revision: 1.2 $
24
--
25
-- ---------------------------------------------------------------------
26

    
27
-- not in book
28

    
29
entity computer_system is
30
end entity computer_system;
31

    
32
-- end not in book
33

    
34

    
35
architecture top_level of computer_system is
36

    
37
  function resolve_bits ( bits : bit_vector ) return bit is
38
    variable result : bit := '0';
39
  begin
40
    for index in bits'range loop
41
      result := result or bits(index);
42
      exit when result = '1';
43
    end loop;
44
    return result;
45
  end function resolve_bits;
46

    
47
  signal write_en : resolve_bits bit bus;
48
  -- . . .
49

    
50
  -- not in book
51
  constant Tpd : delay_length := 2 ns;
52
  signal clock, hold_req : bit := '0';
53
  -- end not in book
54

    
55
begin
56

    
57
  CPU : process is
58
                  -- . . .
59
  begin
60
    write_en <= '0' after Tpd;
61
    -- . . .
62
    loop
63
      wait until clock = '1';
64
      if hold_req = '1' then
65
        write_en <= null after Tpd;
66
        wait on clock until clock = '1' and hold_req = '0';
67
        write_en <= '0' after Tpd;
68
      end if;
69
      -- . . .
70
    end loop;
71
  end process CPU;
72

    
73
  -- . . .
74

    
75
  -- not in book
76

    
77
  clock_gen : clock <= '1' after 5 ns, '0' after 10 ns when clock = '0';
78

    
79
  stimulus : hold_req <= '1' after 40 ns, '0' after 80 ns;
80

    
81
  process is
82
  begin
83
    write_en <= null, '1' after 50 ns, '0' after 60 ns, null after 70 ns;
84
    wait;
85
  end process;
86

    
87
  -- end not in book
88

    
89
end architecture top_level;
(19-19/28)