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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_15_cg-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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architecture behavior of clock_gen is
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  constant clock_period : delay_length := 2 * (Tpw + Tps);
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begin
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  reset_driver : 
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    reset <= '1', '0' after 2.5 * clock_period + Tps;
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  clock_driver : process is
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  begin
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    phi1 <= '0';
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    phi2 <= '0';
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    wait for clock_period / 2;
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    loop
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      phi1 <= '1', '0' after Tpw;
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      phi2 <= '1' after clock_period / 2,
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              '0' after clock_period / 2 + Tpw;
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      wait for clock_period;
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    end loop;
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  end process clock_driver;
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end architecture behavior;
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