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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_07_fg_07_03.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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entity fg_07_03 is
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end entity fg_07_03;
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library bv_utilities;
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architecture interpreter of fg_07_03 is
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  subtype word is bit_vector(31 downto 0);
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  signal address_bus, data_bus_in : word := X"0000_0000";
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  signal mem_read, mem_request, mem_ready : bit := '0';
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begin
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  -- code from book
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  instruction_interpreter : process is
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                                      variable mem_address_reg, mem_data_reg,
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                                    prog_counter, instr_reg, accumulator, index_reg : word;
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                                    -- . . .
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                                    -- not in book
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                                    type opcode_type is (load_mem);
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                                    constant opcode : opcode_type := load_mem;
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                                    constant displacement : word := X"0000_0010";
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                                    use bv_utilities.bv_arithmetic.all;
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                                    -- end not in book
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                                    procedure read_memory is
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                                    begin
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                                      address_bus <= mem_address_reg;
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                                      mem_read <= '1';
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                                      mem_request <= '1';
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                                      wait until mem_ready = '1';
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                                      mem_data_reg := data_bus_in;
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                                      mem_request <= '0';
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                                      wait until mem_ready = '0';
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                                    end procedure read_memory;
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  begin
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    -- . . .  -- initialization
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    loop
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      -- fetch next instruction
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      mem_address_reg := prog_counter;
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      read_memory;                           -- call procedure
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      instr_reg := mem_data_reg;
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      -- . . .
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      case opcode is
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        -- . . .
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        when load_mem =>
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          mem_address_reg := index_reg + displacement;
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          read_memory;                        -- call procedure
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          accumulator := mem_data_reg;
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          -- . . .
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      end case;
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    end loop;
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  end process instruction_interpreter;
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  -- end code from book
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  memory : process is
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  begin
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    wait until mem_request = '1';
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    data_bus_in <= X"1111_1111";
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    mem_ready <= '1';
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    wait until mem_request = '0';
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    mem_ready <= '0';
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  end process memory;
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end architecture interpreter;
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