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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_04_fg_04_01.vhd,v 1.3 2001-11-03 23:19:37 paw Exp $
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-- $Revision: 1.3 $
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--
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-- ---------------------------------------------------------------------
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-- not in book:
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library ch4_pkgs;
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use ch4_pkgs.pk_04_01.all;
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-- end not in book
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entity coeff_ram is
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  port ( rd, wr : in bit;  addr : in coeff_ram_address;
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  d_in : in real;  d_out : out real );
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end entity coeff_ram;
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--------------------------------------------------
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architecture abstract of coeff_ram is
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begin
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  memory : process is
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                     type coeff_array is array (coeff_ram_address) of real;
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                   variable coeff : coeff_array;
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  begin
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    for index in coeff_ram_address loop
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      coeff(index) := 0.0;
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    end loop;
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    loop
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      wait on rd, wr, addr, d_in; 
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      if rd = '1' then
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        d_out <= coeff(addr);
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      end if;
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      if wr = '1' then
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        coeff(addr) := d_in;
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      end if;
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    end loop;
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  end process memory;
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end architecture abstract;
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