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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_21_fg_21_04.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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library ieee;  use ieee.std_logic_1164.all;
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               entity processor is
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               end entity processor;
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-- code from book
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               architecture rtl of processor is
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                 component latch is
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                                   generic ( width : positive );
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                                 port ( d : in std_ulogic_vector(0 to width - 1);
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                                        q : out std_ulogic_vector(0 to width - 1);
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                                        -- . . . );
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                                        -- not in book
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                                        other_port : in std_ulogic := '-' );
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                                 -- end not in book
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                 end component latch;
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                 component ROM is
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                                 port ( d_out : out std_ulogic_vector;  -- . . . );
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                                        -- not in book
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                                        other_port : in std_ulogic := '-' );
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                               -- end not in book
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                 end component ROM;
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                 subtype std_logic_word is std_logic_vector(0 to 31);
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                 signal source1, source2, destination : std_logic_word;
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                 -- . . .
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               begin
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                 temp_register : component latch
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                   generic map ( width => 32 )
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                   port map ( d => std_ulogic_vector(destination),
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                              std_logic_vector(q) => source1, -- . . . );
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                              -- not in book
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                              other_port => open );
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                 -- end not in book
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                 constant_ROM : component ROM
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                   port map ( std_logic_word(d_out) => source2, -- . . . );
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                              -- not in book
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                              other_port => open );
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                 -- end not in book
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                 -- . . .
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               end architecture rtl;
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-- end code from book
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