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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_21_fg_21_01.vhd,v 1.2 2001-10-26 16:29:37 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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entity D_flipflop is
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  port ( clk, d : in bit;  q : buffer bit );
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end entity D_flipflop;
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architecture behavioral of D_flipflop is
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begin
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  q <= d when clk'event and clk = '1';
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end architecture behavioral;
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entity inverter is
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  port ( a : in bit;  y : out bit );
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end entity inverter;
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architecture behavioral of inverter is
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begin
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  y <= not a;
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end architecture behavioral;
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-- code from book
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entity count2 is
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  port ( clk : in bit;  q0, q1 : buffer bit );
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end entity count2;
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--------------------------------------------------
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architecture buffered_outputs of count2 is
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  component D_flipflop is
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                         port ( clk, d : in bit;  q : buffer bit );
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  end component D_flipflop;
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  component inverter is
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                       port ( a : in bit;  y : out bit );
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  end component inverter;
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  signal q0_n, q1_n : bit;
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begin
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  bit0 : component D_flipflop
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    port map ( clk => clk, d => q0_n, q => q0 );
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  inv0 : component inverter
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    port map ( a => q0, y => q0_n );
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  bit1 : component D_flipflop
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    port map ( clk => q0_n, d => q1_n, q => q1 );
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  inv1 : component inverter
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    port map ( a => q1, y => q1_n );
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end architecture buffered_outputs;
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-- end code from book
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entity fg_21_01 is
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end entity fg_21_01;
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architecture test of fg_21_01 is
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  signal clk, q0, q1 : bit;
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begin
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  dut : entity work.count2(buffered_outputs)
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    port map ( clk => clk, q0 => q0, q1 => q1 );
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  clk_gen : clk <= not clk after 10 ns;
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end architecture test;
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