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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_20_fg_20_18.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
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-- $Revision: 1.1.1.1 $
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--
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-- ---------------------------------------------------------------------
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package timing_attributes is
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  attribute max_wire_delay : delay_length;
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end package timing_attributes;
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entity sequencer is
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end entity sequencer;
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-- code from book
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library ieee;  use ieee.std_logic_1164.all;
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use work.timing_attributes.all;
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architecture structural of sequencer is
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  signal recovered_clk1, recovered_clk2 : std_logic;
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  signal test_enable : std_logic;
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  signal test_data : std_logic_vector(0 to 15);
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  attribute max_wire_delay of
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    recovered_clk1, recovered_clk2 : signal is 100 ps;
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  attribute max_wire_delay of others : signal is 200 ps;
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  -- . . .
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begin
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  -- . . .
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  -- not in book
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  assert false report time'image(recovered_clk1'max_wire_delay) severity note;
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  assert false report time'image(recovered_clk2'max_wire_delay) severity note;
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  assert false report time'image(test_enable'max_wire_delay) severity note;
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  assert false report time'image(test_data'max_wire_delay) severity note;
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  -- end not in book
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end architecture structural;
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-- code from book
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