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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
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-- This file is part of VESTs (Vhdl tESTs).
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-- VESTs is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2 of the License, or (at
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-- your option) any later version. 
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-- VESTs is distributed in the hope that it will be useful, but WITHOUT
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-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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-- FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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-- for more details. 
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-- You should have received a copy of the GNU General Public License
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-- along with VESTs; if not, write to the Free Software Foundation,
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-- Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
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-- ---------------------------------------------------------------------
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--
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-- $Id: ch_20_fg_20_14.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
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-- $Revision: 1.2 $
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--
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-- ---------------------------------------------------------------------
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package graphics_pkg is
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  attribute graphic_symbol : string;
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  attribute graphic_style : string;
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end package graphics_pkg;
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-- code from book
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library ieee;  use ieee.std_logic_1164.all;
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--library graphics;
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library work;
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package gate_components is
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  --use graphics.graphics_pkg.graphic_symbol,
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  -- graphics.graphics_pkg.graphic_style;
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  use work.graphics_pkg.all;
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  component and2 is
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                   generic ( prop_delay : delay_length );
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                 port ( a, b : in std_logic;  y : out std_logic );
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  end component and2;
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  attribute graphic_symbol of and2 : component is "and2";
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  attribute graphic_style of and2 : component is "color:default, weight:bold";
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  -- . . .
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end package gate_components;
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-- end code from book
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